- 您現在的位置：買賣IC網 > PDF目錄373969 > AD9874 (ANALOG DEVICES INC) IF Digitizing Subsystem PDF資料下載
參數資料
| 型號： | AD9874 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | IF Digitizing Subsystem |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | 1.40 MM HEIGHT, PLASTIC, TQFP-48 |
| 文件頁數： | 27/40頁 |
| 文件大?。?/td> | 744K |
| 代理商： | AD9874 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
REV. 0
AD9874
–27–
VARIABLE GAIN AMPLIFIE R OPE RAT ION WIT H
AUT OMAT IC GAIN CONT ROL
The AD9874 contains both a variable gain amplifier (VGA) and
a digital VGA (DVGA) along with all of the necessary signal estima-
tion and control circuitry to implement automatic gain control
(AGC), as shown in Figure 18. The AGC control circuitry provides
a high degree of programmability, allowing users to optimize the
AGC response as well as the AD9874’s dynamic range for a given
application. The VGA is programmable over a 12 dB range and
implemented within the ADC by adjusting its full-scale reference
level. Increasing the ADC’s full scale is equivalent to attenuating
the signal. An additional 12 dB of digital gain range is achieved
by scaling the output of the decimation filter in the DVGA. Note,
a slight increase in the supply current (i.e., 0.67 mA) is drawn from
VDDI and VDDF as the VGA changes from 0 dB to 12 dB attenuation.
The purpose of the VGA is to extend the usable dynamic range
of the AD9874 by allowing the ADC to digitize a desired signal
over a large input power range as well as recover a low level signal
in the presence of larger unfiltered interferers without saturating
or “clipping” the ADC. The DVGA is most useful in extending
the dynamic range in narrow-band applications requiring a 16-bit
I and Q data format. In these applications, quantization noise
resulting from internal truncation to 16 bits as well as external
16-bit fixed point post-processing can degrade the AD9874’s
effective noise figure by 1 or more dB. The DVGA is enabled by
writing a 1 to the AGCV field. The VGA (and the DVGA) can
operate in either a user-controlled Variable Gain Mode or Auto-
matic Gain Control (AGC) Mode.
It is worth noting that the VGA imparts negligible phase error
upon the desired signal as its gain is varied over a 12 dB range.
This is due to the bandwidth of the VGA being far greater than
the down converted desired signal (centered about f
CLK
/8) and
remaining relatively independent of gain setting. As a result, phase
modulated signals should experience minimal phase error as the
AGC varies the VGA gain while tracking an interferer or the desired
signal under fading conditions. Note, the envelope of the signal
will still be affected by the AGC settings.
Variable Gain Control
The variable gain control is enabled by setting the AGCR field
of Register 0x06 to 0. In this mode, the gain of the VGA (and the
DVGA) can be adjusted by writing to the 16-bit AGCG Register.
The maximum update rate of the AGCG Register via the SPI port
is
f
CLK
/240. The MSB of this register is the bit that enables 16 dB
of attenuation in the mixer. This feature allows the AD9874 to
cope with large level signals beyond the VGA’s range (i.e.,
> –18 dBm at LNA input) to prevent overloading of the ADC.
The lower 15 bits specify the attenuation in the remainder of the
signal path. If the DVGA is enabled, the attenuation range is from
–12 dB to +12 dB since the DVGA provides 12 dB of digital gain.
In this case, all 15 bits are significant. However, with the DVGA
disabled the attenuation range extends from 0 dB to 12 dB and
only the lower 14 bits are useful. Figure 19 shows the relationship
between the amount of attenuation and the AGC Register setting
for both cases.
AGCG SETTING – HEX
–12
0
12
0000
A
1FFF
3FFF
7FFF
5FFF
6
–6
VGA
RANGE
DVGA
RANGE
ONLY
VGA ENABLED
DVGA AND
VGA ENABLED
Figure 19. AGC Gain Range Characteristics vs. AGCG
Register Setting with and without DVGA Enabled
+
VGA
DAC
-
ADC
FS
DEC1
12
DEC2
AND
DEC3
I + Q
I + Q
SELECT
LARGER
AGCR
REF LEVEL
K
AGCA/AGCD
SCALING
C
DAC
GCP
1
(1 – Z
–1
)
AGCV
SETTING
DVGA
RSSI DATA
TO SSI
I/Q DATA
TO SSI
Figure 18. Functional Block Diagram of VGA and AGC
相關PDF資料 |
PDF描述 |
|---|---|
| AD9874BST | IF Digitizing Subsystem |
| AD9874EB | IF Digitizing Subsystem |
| AD9875BSTRL | Broadband Modem Mixed-Signal Front End |
| AD9875 | Broadband Modem Mixed-Signal Front End |
| AD9875-EB | Broadband Modem Mixed-Signal Front End |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9874ABST | 功能描述:IC IF DIGIT SUBSYSTEM 48-LQFP RoHS:否 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標準包裝:100 系列:* |
| AD9874ABST | 制造商:Analog Devices 功能描述:IF DIGITIZING SYBSYSTEM ((NW)) 制造商:Analog Devices 功能描述:IC, IF DIGITIZING SUBSYSTEM, LQFP-48 |
| AD9874ABST | 制造商:Analog Devices 功能描述:IC IF DIG SUBSYSTEM |
| AD9874ABSTRL | 功能描述:IC IF DIGIT SUBSYSTEM 48-LQFP RoHS:否 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標準包裝:100 系列:* |
| AD9874ABSTZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Digitizing Subsystem |
發布緊急采購，3分鐘左右您將得到回復。