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參數資料
| 型號： | AD9874 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | IF Digitizing Subsystem |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | 1.40 MM HEIGHT, PLASTIC, TQFP-48 |
| 文件頁數： | 24/40頁 |
| 文件大小： | 744K |
| 代理商： | AD9874 |
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REV. 0
–24–
AD9874
The signal transfer function of the AD9874 possesses inherent
antialias filtering by virtue of the continuous-time portions of the
loop filter in the band-pass - modulator. Figure 13b illustrates
this property by plotting the nominal signal transfer function of the
ADC for frequencies up to
2f
CLK
. The notches that naturally occur
for all frequencies that alias to the
f
CLK
/8 pass band are clearly
visible. Even at the widest bandwidth setting, the notches are deep
enough to provide greater than 80 dB of alias protection. Thus,
the wideband IF filtering requirements preceding the AD9874
will be mostly determined by the mixer’s image band that is offset
from the desired IF input frequency by
f
CLK
/4 (i.e., 2
f
CLK
/8),
rather than any aliasing associated with the ADC.
0
0
–10
–20
–30
–50
d
–40
NORMALIZED FREQUENCY – RELATIVE TO
f
OUT
–60
–70
–80
0.5
1.0
1.5
2.0
NOTCH AT ALL ALIAS FREQUENCIES
Figure 13b. Signal Transfer Function of the Band-Pass
-
Modulator from 0 f
CLK
to 2 f
CLK
Figure 13c shows the nominal signal transfer function magnitude
for frequencies near the
f
CLK
/8 pass band. The width of the pass
band determines the transfer function droop, but even at the
lowest oversampling ratio (48) where the pass band edges are at
f
CLK
/192 ( .005
f
CLK
),
the gain variation is less than 0.5 dB.
Note, the amount of attenuation offered by the signal transfer
function near
f
CLK
/8 should also be considered when determining
the narrow-band IF filtering requirements preceding the AD9874.
–0.1
0
–5
d
–10
NORMALIZED FREQUENCY – RELATIVE TO
f
CLK
–15
–20
–0.05
0
0.05
0.1
Figure 13c. Magnitude of the ADC’s Signal Transfer
Function near f
CLK
/8
Tuning of the
-
modulator’s two continuous-time resonators
is essential in realizing the ADC’s full dynamic range and must
be performed upon system startup. To facilitate tuning of the
LC tank, a capacitor array is internally connected to the MXOP
and MXON pins. The capacitance of this array is programmable
from 0 pF to 200 pF
±
20% and can be programmed either
automatically or manually via the SPI port. The capacitors of
the active RC resonator are similarly programmable. Note, the
AD9874 can be placed in and out of its standby mode without
retuning since the tuning codes are stored in the SPI Registers.
When tuning the LC tank, the sampling clock frequency must
be stable and the LNA/mixer, LO synthesizer, and ADC must
all be placed in standby. Tuning is triggered when the ADC is
taken out of standby if the TUNE_LC bit of register 0x1C has
been set. This bit will clear when the tuning operation is complete
(less than 6 ms). The tuning codes can be read from the 3-bit
CAPL1 (0x1D) and the 6-bit CAPL0 (0x1E) Registers.
In a similar manner, tuning of the RC resonator is activated if
the TUNE_RC bit of register 0x1C is set when the ADC is taken
out of standby. This bit will clear when tuning is complete. The
tuning code can be read from the CAPR (0x1F) Register. Setting
both the TUNE_LC and TUNE_RC bits tunes the LC tank and
the active RC resonator in succession. During tuning, the ADC
is not operational and neither data nor a clock is available from
the SSI port. Table X lists the recommended sequence of the
SPI commands for tuning the ADC, while Table XI lists all of
the SPI Registers associated with band-pass - ADC.
Table X. Tuning Sequence
Address
Value
Comments
0x01
0x45
LO synthesizer, LNA/mixer, and ADC are
placed in standby.
*
0x01
0x03
Set TUNE_LC and TUNE_RC. Wait for
CLK to stabilize if CLK synthesizer used.
0x03
0x44
Take the ADC out of standby. Wait for 0x1C to
clear (<6 ms). LNA/mixer can now be taken
out of standby.
*
If external CLK VCO or source used, the CLK oscillator must also be disabled.
Table XI. SPI Registers Associated with Band-Pass - ADC
Address
(Hex)
Bit
Breakdown
Default
Value
Width
Name
0x00
(7:0)
8
0xFF
STBY
0x1C
(1)
(0)
1
1
0
0
TUNE_LC
TUNE_RC
0x1D
(2:0)
3
0
CAPL1(2:0)
0x1E
(5:0)
6
0x00
CAPL1(5:0)
0x1F
(7:0)
8
0x00
CAPR
相關PDF資料 |
PDF描述 |
|---|---|
| AD9874BST | IF Digitizing Subsystem |
| AD9874EB | IF Digitizing Subsystem |
| AD9875BSTRL | Broadband Modem Mixed-Signal Front End |
| AD9875 | Broadband Modem Mixed-Signal Front End |
| AD9875-EB | Broadband Modem Mixed-Signal Front End |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9874ABST | 功能描述:IC IF DIGIT SUBSYSTEM 48-LQFP RoHS:否 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標準包裝:100 系列:* |
| AD9874ABST | 制造商:Analog Devices 功能描述:IF DIGITIZING SYBSYSTEM ((NW)) 制造商:Analog Devices 功能描述:IC, IF DIGITIZING SUBSYSTEM, LQFP-48 |
| AD9874ABST | 制造商:Analog Devices 功能描述:IC IF DIG SUBSYSTEM |
| AD9874ABSTRL | 功能描述:IC IF DIGIT SUBSYSTEM 48-LQFP RoHS:否 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標準包裝:100 系列:* |
| AD9874ABSTZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Digitizing Subsystem |
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