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參數資料
| 型號： | AD9874 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | IF Digitizing Subsystem |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | 1.40 MM HEIGHT, PLASTIC, TQFP-48 |
| 文件頁數： | 20/40頁 |
| 文件大小： | 744K |
| 代理商： | AD9874 |
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REV. 0
–20–
AD9874
The bias, I
BIAS
, of the negative-resistance core has four pro-
grammable settings. Lower equivalent Q of the LC tank circuit
may require a higher bias setting of the negative-resistance core
to ensure proper oscillation. R
BIAS
should be selected so the
common-mode voltage at CLKP and CLKN is approximately
1.6 V. The synthesizer may be disabled via the CK standby bit
to allow the user to employ an external synthesizer and/or VCO
in place of those resident on the IC. Note, if an external CLK
source or VCO is used, the clock oscillator must be disabled via
the CKO standby bit.
The phase noise performance of the clock synthesizer is depen-
dent on several factors, including the CLK oscillator I
BIAS
setting, the charge pump setting, the loop filter component
values, and the internal f
REF
setting. Figures 7b and 7c show
how the measured phase noise attributed to the clock synthe-
sizer varies (relative to an external f
CLK
) as a function of the
I
BIAS
setting and charge pump setting for a –31 dBm IFIN signal
at 73.35 MHz with an external LO signal at 71.1 MHz. Figure
7b shows that the optimum phase noise is achieved with the
highest I
BIAS
(CKO) setting, while Figure 7c shows that the
higher charge pump values provide the optimum performance
for the given loop filter configuration. The AD9874 clock syn-
thesizer and oscillator were set up to provide a f
CLK
of 18 MHz
from an external f
REF
of 16.8 MHz. The following external
component values were selected for the synthesizer: R
F
= 390
,
R
D
= 2 k
, C
Z
= 0.68
μ
F, C
P
= 0.1
μ
F, C
OSC
= 91 pF, L
OSC
=
1.2
μ
H, and C
VAR
= Toshiba 1SV228 Varactor.
–25
0
–90
–100
–110
–120
d
–20
–15
–10
FREQUENCY OFFSET – kHz
–5
0
5
10
15
20
25
CKO = 0
–80
–70
–60
–50
–40
–30
–20
–10
CKO = 1
CKO = 2
EXT CLK
Figure 7b. CLK Phase Noise vs. I
BIAS
Setting (CKO)
(CLK SYN Settings: CKI = 7, CLR = 56, and CLN = 60
with f
REF
= 100kHz)
CLOCK SYNTHESIZER
The clock synthesizer is a fully programmable integer-
N
PLL
capable of 2.2 kHz resolution at clock input frequencies up to
18 MHz and reference frequencies up to 25 MHz. It is similar
to the LO synthesizer described previously in Figure 4 with the
following exceptions:
It does not include an 8/9 prescaler nor an A counter.
It includes a negative-resistance core that when used in conjunc-
tion with an external LC tank and varactor, serves as the VCO.
The 14-bit reference counter and 13-bit N-divider counter
can
be programmed via the following registers: CKR and CKN.
The clock frequency,
f
CLK
, is related to the reference
frequency by the following equation:
=
(
The charge pump current is programmable via the CKI register
from 0.625 mA to 5.0 mA using the following equation:
I
The fast acquire subcircuit of the charge pump is controlled by
the CKFA Register in the same manner as the LO synthesizer is
controlled by the LOFA Register. An on-chip lock detect function
(enabled by the CKF bit) automatically increases the output
current for faster settling during channel changes. The synthe-
sizer may also be disabled using the CK standby bit located in
the STBY Register.
f
CKN CKR
f
CLK
REF
)
×
(5)
CKI
(
mA
PUMP
=
+
)
×
1
0 625
.
(6)
2
CLK OSC. BIAS
I
= 0.15 mA, 0.25 mA,
0.40 mA, OR 0.65 mA
VDDC = 3.0 V
IOUTC
L
OSC
0.1 F
R
BIAS
C
OSC
LOOP
FILTER
C
VAR
R
D
AD9874
CLKN
CLKP
V
CM
= VDDC – R
BIAS
I
BIAS
> 1.6V
f
OSC
> 1/{2
(L
OSC
(C
VARACTOR
//C
OSC
))
1/2
}
C
P
C
Z
R
F
Figure 7a. External Loop Filter, Varactor, and LC Tank
Are Required to Realize a Complete Clock Synthesizer
The AD9874 clock synthesizer circuitry includes a negative-
resistance core so that only an external LC tank circuit with a
varactor is needed to realize a voltage controlled clock oscillator
(VCO). Figure 7a shows the external components required to
complete the clock synthesizer along with the equivalent input
circuitry of the CLK input. The resonant frequency of the VCO
is approximately determined by L
OSC
and the series equivalent
capacitance of C
OSC
and C
VAR
. As a result, L
OSC
, C
OSC
, and
C
VAR
should be selected to provide a sufficient tuning range to
ensure proper locking of the clock synthesizer.
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| AD9874BST | IF Digitizing Subsystem |
| AD9874EB | IF Digitizing Subsystem |
| AD9875BSTRL | Broadband Modem Mixed-Signal Front End |
| AD9875 | Broadband Modem Mixed-Signal Front End |
| AD9875-EB | Broadband Modem Mixed-Signal Front End |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9874ABST | 功能描述:IC IF DIGIT SUBSYSTEM 48-LQFP RoHS:否 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標準包裝:100 系列:* |
| AD9874ABST | 制造商:Analog Devices 功能描述:IF DIGITIZING SYBSYSTEM ((NW)) 制造商:Analog Devices 功能描述:IC, IF DIGITIZING SUBSYSTEM, LQFP-48 |
| AD9874ABST | 制造商:Analog Devices 功能描述:IC IF DIG SUBSYSTEM |
| AD9874ABSTRL | 功能描述:IC IF DIGIT SUBSYSTEM 48-LQFP RoHS:否 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標準包裝:100 系列:* |
| AD9874ABSTZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Digitizing Subsystem |
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