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參數資料
| 型號： | AFE7222EVM |
| 廠商： | Texas Instruments |
| 文件頁數： | 26/106頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL MODULE FOR AFE7222 |
| 標準包裝： | 1 |
| 主要目的： | 接口，模擬前端（AFE） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AFE7222 |
| 已供物品： | 板 |
| 其它名稱： | 296-30300 AFE7222EVM-ND |
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SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
Register Name – CONFIG8 – Address 0x10D, Default = 0x00
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TX_GLOBAL_SER_
TX_QMC_GAIN_PH_
TX_QMC_OFF_
TX_DIV_SER_
TX_CMIX_SER_
TX_FIFO_SER_
IF_SYNC
SER_IF_SYNC
IF_SYNC
TX_FIFO_SER_IF_SYNC – A rising edge on this bit is used as the sync source for TX FIFO. This is
applicable
when
TX_GLOBAL_SYNC_DIS
is
set,
and
TX_FIFO_SYNC_DIS
is
cleared,
and
TX_FIFO_SYNC_SRC specifies serial interface bit to be the sync source for the FIFO.
TX_CMIX_SER_IF_SYNC – A rising edge on this bit is used as the sync source for TX CMIX. This is
applicable
when
TX_GLOBAL_SYNC_DIS
is
set,
and
TX_CMIX_SYNC_DIS
is
cleared,
and
TX_CMIX_SYNC_SRC specifies serial interface bit to be the sync source for the TX CMIX.
TX_DIV_SER_IF_SYNC – A rising edge on this bit is used as the sync source for TX Divider. This is
applicable
when
TX_GLOBAL_SYNC_DIS
is
set,
and
TX_DIV_SYNC_DIS
is
cleared,
and
TX_DIV_SYNC_SRC specifies serial interface bit to be the sync source for the TX Divider.
TX_QMC_OFF_SER_IF_SYNC – A rising edge on this bit is used as the sync source for TX QMC Offset
correction block. This is applicable when TX_GLOBAL_SYNC_DIS is set, and TX_QMC_OFF_SYNC_DIS
is cleared, and TX_QMC_OFF_SYNC_SRC specifies serial interface bit to be the sync source for the TX
QMC Offset correction.
TX_QMC_GAIN_PH_SER_IF_SYNC – A rising edge on this bit is used as the sync source for TX QMC
Gain
Phase
correction
block.
This
is
applicable
when
TX_GLOBAL_SYNC_DIS
is
set,
and
TX_QMC_GAIN_PH_SYNC_DIS is cleared, and TX_QMC_GAIN_PH_SYNC_SRC specifies serial
interface bit to be the sync source for the TX QMC Gain Phase correction.
TX_GLOBAL_SER_IF_SYNC – A rising edge on this is used as the sync source for TX. This is applicable
when TX_GLOBAL_SYNC_DIS is cleared, and TX_GLOBAL_SYNC_SRC(1:0) specifies serial interface
bit to be the sync source for TX.
Register Name – CONFIG9 – Address 0x10E, Default = 0x00
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TX_QMC_CORR_
TX_QMC_OFFSET_
TX_QMC_GAIN_PH_
TX_QMC_OFF_
ENA
SYNC_NEEDED
TX_QMC_OFF_SYNC_NEEDED – Specifies if syncing is needed for TX QMC Offset Correction . If set,
QMC Offset values programmed in the serial interface registers are not applied to the QMC Offset
correction block until a sync is applied.
TX_QMC_GAIN_PH_SYNC_NEEDED – Specifies if syncing is needed for TX QMC Gain Phase
Correction. If set, QMC gain and Phase values programmed into the serial interface registers are not
applied to the QMC Gain Phase correction block until a sync is applied.
TX_QMC_OFFSET_ENA – Enables TX QMC Offset Correction. Common for both channels.
TX_QMC_CORR_ENA – Enable TX QMC Gain Phase Correction. Common for both channels. Note that
by
default,
the
TX_QMC_GAINA(2:0)
and
TX_QMC_GAINB(2:0)
are
set
to
0.
So
when
TX_QMC_CORR_ENA is written, the output goes to zero until the time TX_QMC_GAINA(2:0) and
TX_QMC_GAINB(2:0) are written to the desired value.
Register Name – CONFIG10 – Address 0x10F Default = 0x00 (Optionally Synced)
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
TX_QMC_OFFSETA(12:5)
TX_QMC_OFFSETA(12:5) – Upper 8 bits of DAC A Offset Correction . The lower 5 bits are in CONFIG11
Register. Offset is a signed value (2s complement).
26
REGISTER DESCRIPTIONS
Copyright 2011–2012, Texas Instruments Incorporated
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