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參數資料
| 型號： | AFE7222EVM |
| 廠商： | Texas Instruments |
| 文件頁數： | 84/106頁 |
| 文件大小： | 0K |
| 描述： | EVAL MODULE FOR AFE7222 |
| 標準包裝： | 1 |
| 主要目的： | 接口，模擬前端（AFE） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AFE7222 |
| 已供物品： | 板 |
| 其它名稱： | 296-30300 AFE7222EVM-ND |
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S
13
QMC_OFFSETA
A Data In
S
13
QMC_OFFSETB
B Data In
A Data Out
B Data Out
12
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
9.16 DIGITAL OFFSET CONTROL
Registers QMC_OFFSETA(12:0) and QMC_OFFSETB(12:0) control the A and B path offsets and are 13-
bit values with a range of -4096 to 4095. The offset adjustment value is got by dividing the register value
by 16, so the range of the offset adjustment is ±256 LSB. The DAC offset value adds a digital offset to the
digital data before digital-to-analog conversion. The data and offset values are LSB aligned.
Figure 9-13. Digital Offset Block Diagram
9.17 SYNCHRONIZING MULTIPLE CHIPS
The AFE722x has a SYNC pin that can be used to synchronize multiple chips. When such synchronization
is not required, the SYNC pin can be tied to ground (or in the case of differential SYNC input, tie
SYNCINP to logic low and SYNCINN to logic high).
On the transmit side, several blocks need to be synchronized. These include the clock divider, FIFO read
and write pointersm, coarse mixer mixing phase, NCO phase, power meter, QMC gain/ phase correction
block. Note however that all these blocks can function even without synchronization.
The simplest way to synchronize all blocks is using the global synchronizing mode, which is enabled by
default. The synchronization source, by default, is the SYNC pin. A rising edge on the SYNC pin will
cause all blocks to be synced in an order that is internally controlled. The synchronization source can also
be set to a serial interface bit (TX_GLOBAL_SYNC_SRC and RX_GLOBAL_SYNC_SRC). When using
the serial interface bit, a 0-1 transition on the register bit triggers syncing.
In most cases, global synchronizing mode is sufficient. However, each block can be independently
synchronized
by
disabling
the
global
synchronization
modes
(TX_GLOBAL_SYNC_DIS
and
RX_GLOBAL_SYNC_DIS) and enabling the block-specific synchronization register controls. The block-
specific synchronization can also be done either using the SYNC pin or using 0-1 transitions on specific
register bits.
For some blocks, there is an option to specify whether or not syncing is neede. An example is the QMC
offset register control. When syncing is specified as not needed, the values in the QMC offset register are
applied as soon as they are written into. However when syncing is specified as needed, the values written
into this register are applied to the block only when a valid SYNC pulse is applied.
When applying block specific syncing, it is recommended that the following order be followed:
1. Synchronize the clock divider first
2. Synchronize the FIFO next
3. Synchronize all other other blocks next in no specific order
The effect on synchronizing on various blocks is listed below:
FIFO – the write pointer is reset to zero and the read pointer is reset to 4.
QMC offset correction – The QMC offset correction values programmed into the serial interface
registers are loaded into the block
QMC Gain/ Phase correction block – The gain and phase correction values programmed into the
serial interface registers are loaded into the block
Copyright 2011–2012, Texas Instruments Incorporated
APPLICATION INFORMATION
79
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