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參數資料
| 型號： | AFE7222EVM |
| 廠商： | Texas Instruments |
| 文件頁數： | 46/106頁 |
| 文件大小： | 0K |
| 描述： | EVAL MODULE FOR AFE7222 |
| 標準包裝： | 1 |
| 主要目的： | 接口，模擬前端（AFE） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AFE7222 |
| 已供物品： | 板 |
| 其它名稱： | 296-30300 AFE7222EVM-ND |
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SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
5.3
CHIP CONTROL REGISTERS
Register Name – CONFIG107 – Address 0x000, Default = 0x00
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
SOFTWARE_RESET
SOFTWARE_RESET:-Register bit to reset the device. Once set, the bit generates a reset pulse, which
resets all the register bits including itself.
Register Name – CONFIG108 – Address 0x207, Default = 0x00
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
REG_PDNFRM_REG
REG_PDN_FAST
REG_PDN_GBL
REG_PDNQ
REG_PDNI
REG_PDN_RX
REG_PDN_TX
REG_PDN_FRM_REG : Specifies whether the PDN control is through PIN or register bit. When cleared,
PDN pin is used as the master control.
For all the below power down modes to work, either set REG_PDN_FRM_REG or pull PDN pin to ‘High’.
REG_PDN_FAST : When REG_PDN_FRM_REG is low, this bit configures the PDN pin for fast
powerdown control. When REG_PDN_FRM_REG is high, this bit directly controls the fast powerdown
mode. When set, it power downs both transmitter and receiver but keeps certain blocks like reference
circuitry active. Also the Rx output clock is still active. This mode can be used where fast wake up times
are required.
REG_PDN_GBL : When REG_PDN_FRM_REG is low, this bit configures the PDN pin for global
powerdown control. When REG_PDN_FRM_REG is high, this bit directly controls the global powerdown
mode. When set, it powers down almost all circuitry inside the chip. Thus this mode can be used when
lowest power is desired. The wakeup times in this mode are much higher than in the fast powerdown
mode.
REG_PDNQ : Power downs Q channel of both transmitter and reciever.
REG_PDNI : Power down I channel of both transmitter and reciever.
REG_PDN_RX : Power downs reciever i.e both the ADC’s. Clock path is still active.
REG_PDN_TX : Power downs transmitter i.e both the DAC’s.
REG_PDN_FRM_REG has a similar role to play for the above modes (REG_PDNQ, REG_PDNI,
REG_PDN_RX, REG_PDN_TX). When REG_PDN_FRM_REG is low, it configures the PDN pin to the
function of the bit that is set. When REG_PDN_FRM_REG is high, the set bit directly controls the
described powerdown mode.
At 20 MHz Fs, the typical power consumption in different modes are as follows:
CURRENT ON 1.8 V SUPPLY
CURRENT ON 3 V SUPPLY
CONDITION
(mA)
Normal
63
58
Global Power down (REG_PDN_GBL = 1)
2.4
3
Fast power down (REG_PDN_FAST = 1)
25
13
Rx_power down (REG_PDN_RX = 1)
27
58
Tx power down (REG_PDN_TX = 1)
62
13
Both Rx and Tx (REG_PDN_TX = 1, REG_PDN_RX = 1)
25
13
Register Name – CONFIG109 – Address 0x208, Default = 0x00
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
REG_PDNI_TX
REG_PDNQ_TX
REG_PDNI_RX
REG_PDNQ_RX
MODE_LP_CMOS
REG_SINGLE
44
REGISTER DESCRIPTIONS
Copyright 2011–2012, Texas Instruments Incorporated
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