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參數資料
| 型號： | AFE7222EVM |
| 廠商： | Texas Instruments |
| 文件頁數： | 94/106頁 |
| 文件大小： | 0K |
| 描述： | EVAL MODULE FOR AFE7222 |
| 標準包裝： | 1 |
| 主要目的： | 接口，模擬前端（AFE） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AFE7222 |
| 已供物品： | 板 |
| 其它名稱： | 296-30300 AFE7222EVM-ND |
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CLKINP
CLKINN
Clock
Divider
%1,2,4
Clock
Divider
%1,2,4
PLL
X2,4
ADC_CLK
DAC_CLK
MUX
PLL_ENABLE
REG_SE_CLK
DIV_ADC<1:0>
DIV_DAC<1:0>
DCC
(Duty Cycle
Correction)
MUX
ENABLE_DCC
Single-
ended
Buffer
Single-
ended
Buffer
Differential
Buffer
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
10.7.2 CLOCKING
The clock inputs are versatile. The AFE7225/7222 can be driven by a differential clock, a single-ended
clock or two independent single-ended clocks. Low voltage CMOS for single-ended and LVDS for
differential are supported clock levels. Since routing single-ended clocks on the printed circuit board is
different from system to system, it is possible to see some performance degradation in the data converters
if the clock becomes corrupted prior to entering the AFE7225/7222. This is less likely to occur if using a
differential clock routed on the board due to the common-mode noise rejection of the differential clock
receiver.
The full block diagram of the clocking to the ADC and DAC is shown below.
Figure 10-13. Clocking
Depending on the ADC input frequency and the target SNR of the receiver, it may be important to provide
a low jitter clock source to the AFE7225/7222. A good estimate for required clock jitter to achieve a certain
SNR can be found using SNR = 20*log10(2*pi*FINadc *JITTERtotal). The JITTERtotal is the rms
summation of the external clock jitter and the internal AFE7225/7222 RX ADC clocking aperture jitter,
specified in the timing characteristics table. A good target for the total jitter is a value that allows an SNR
that meets or exceeds the ADC SNR so that the clock source jitter will not degrade the SNR. Note that the
SNR is dependent on the analog input frequency and not the clock frequency.
When different rate clocks are required for the ADC and the DAC (for example, DAC_CLK is 2X rate of
ADC_CLK), it is strongly recommended that the input clock be at the higher of the two rates. Dividing the
high speed clock to derive the half rate clock always gives much lower jitter than using the PLL to multiply
the lower rate clock to derive the higher rate inside the chip. Use the PLL only when performance
requirements are relaxed and the additional jitter is tolerable (usually when the analog I/O frequencies are
low).
The equivalent circuit model of the differential buffer is shown below. Note that even with the single ended
buffer is enabled, the loading from the passive components in the differential buffer circuit (including the 2
pF differential cap, the two 5 kOhm resistors and the equivalent input load, Ceq are still present).
88
DIGITAL INTERFACE
Copyright 2011–2012, Texas Instruments Incorporated
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相關代理商/技術參數 |
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| AFE7222IRGC25 | 功能描述:射頻前端 Dual 12B,65MSPS ADC RoHS:否 制造商:Skyworks Solutions, Inc. 類型: 工作頻率:2.4 GHz, 5 GHz 最大數據速率:54 Mbps 噪聲系數: 工作電源電壓:3.3 V 電源電流:180 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-32 |
| AFE7222IRGCR | 功能描述:射頻前端 Dual 12B,65MSPS ADC RoHS:否 制造商:Skyworks Solutions, Inc. 類型: 工作頻率:2.4 GHz, 5 GHz 最大數據速率:54 Mbps 噪聲系數: 工作電源電壓:3.3 V 電源電流:180 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-32 |
| AFE7222IRGCT | 功能描述:射頻前端 Dual 12B,65MSPS ADC RoHS:否 制造商:Skyworks Solutions, Inc. 類型: 工作頻率:2.4 GHz, 5 GHz 最大數據速率:54 Mbps 噪聲系數: 工作電源電壓:3.3 V 電源電流:180 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-32 |
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| AFE7225EVM | 功能描述:射頻開發工具 AFE7225 Eval Mod RoHS:否 制造商:Taiyo Yuden 產品:Wireless Modules 類型:Wireless Audio 工具用于評估:WYSAAVDX7 頻率: 工作電源電壓:3.4 V to 5.5 V |
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