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參數資料
型號: AFE7222EVM
廠商: Texas Instruments
文件頁數: 74/106頁
文件大小: 0K
描述: EVAL MODULE FOR AFE7222
標準包裝: 1
主要目的: 接口,模擬前端(AFE)
嵌入式:
已用 IC / 零件: AFE7222
已供物品:
其它名稱: 296-30300
AFE7222EVM-ND
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
Table 2-2. Pin Configuration: LVDS Input/Output Mode (continued)
PIN
DESCRIPTION
NO.
NAME
9
CLKINP
main clock input, positive side if differential mode, RX side if single-ended 2 clock mode
10
DVDD18_CLK
1.8V supply for Clocking circuit
11
AVDD3_DAC
3V supply for TX DACs
12
IOUTP_A_DAC
TX DAC channel A current output, positive (current sink DACs)
13
IOUTN_A_DAC
TX DAC channel A current output, negative (current sink DACs)
14
AVDD3_DAC
3V supply for TX DACs
15
IOUTP_B_DAC
TX DAC channel B current output, positive (current sink DACs)
16
IOUTN_B_DAC
TX DAC channel B current output, negative (current sink DACs)
17
AVDD3_DAC
3V supply for TX DACs
sets the TX DAC output current (resistor from pin to ground). Use 960 Ohm to set a full scale current of
18
BIASJ
20 mA.
19
DVDD18_DAC
1.8V DAC digital supply
20
AUXDAC_A
auxiliary DAC channel A output, current sourcing up to 7.5mA (SPI programmable)
21
AUXDAC_B
auxiliary DAC channel B output, current sourcing up to 7.5mA (SPI programmable)
22
AVDD3_AUX
3V supply for auxiliary ADC/DACs
23
AUXADC_A
auxiliary ADC channel A input
24
AUXADC_B
auxiliary ADC channel B input
25
AVDD18_ADC
1.8V supply for RX ADCs
26, 27
LVDS Wire 1 data input for Channel A TX data – inactive in 1-wire mode, LSB byte in 2-wire mode
26
DAC_DATA_11
Positive
27
DAC_DATA_10
Negative
28, 29
LVDS Wire 0 data input for Channel A TX data – active in 1-wire mode, MSB byte in 2-wire mode
28
DAC_DATA_9
Positive
29
DAC_DATA_8
Negative
30, 31
LVDS frame clock input
30
DAC_FCLKINP
Positive
31
DAC_FCLKINN
Negative
32
DVDD18
1.8V supply for digital interface
33, 34
LVDS bit clock input
33
DAC_DCLKINP
Positive
34
DAC_DCLKINN
Negative
35, 36
LVDS Wire 0 data input for Channel B TX data – active in 1-wire mode, LSB byte in 2-wire mode
35
DACB_DATA_0P
Positive
36
DACB_DATA_0N
Negative
37, 38
LVDS Wire 1 data input for Channel B TX data – inactive in 1-wire mode, MSB byte in 2-wire mode
37
DACB_DATA_1P
Positive
38
DACB_DATA_1N
Negative
39, 40
LVDS SYNC input – Used to reset internal clock dividers and reset TX data FIFO pointer
39
SYNCINP
Positive
40
SYNCINN
Negative
41
DVDD18
1.8V supply for digital interface
42, 43
LVDS Wire 1 data output for Channel B RX data – inactive in 1-wire mode, MSB byte in 2-wire mode
42
ADCB_DATA_1N
Positive
43
ADCB_DATA_1P
Negative
44, 45
LVDS Wire 0 data output for Channel B RX data – active in 1-wire mode, LSB byte in 2-wire mode
44
ADCB_DATA_0N
Positive
45
ADCB_DATA_0P
Negative
Copyright 2011–2012, Texas Instruments Incorporated
DEVICE INFORMATION
7
Product Folder Link(s): AFE7222 AFE7225
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