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| 型號： | ARM720T |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | General-purpose 32-bit Microprocessor with 8KB cache, enlarged Write buffer, and Memory Management Unit (MMU) combined in a single chip |
| 中文描述： | 通用32位微處理器與8KB的高速緩存，擴大寫入緩沖區(qū)和內(nèi)存管理單元（MMU）在單一芯片上結(jié)合 |
| 文件頁數(shù)： | 137/242頁 |
| 文件大小： | 831K |
| 代理商： | ARM720T |
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Debug Interface
ARM DDI 0192A
Copyright ARM Limited 1997, 1998, 2000. All rights reserved.
7-27
All these instructions are said to execute at
debug speed
. Debug speed is much slower
than system speed because between each core clock, 33 scan clocks occur to shift in an
instruction, or shift out data. Executing instructions more slowly than usual is
acceptable for accessing the core state because ARM7TDM is fully static. However,
this same method cannot be used for determining the state of the rest of the system.
7.9.3
Determining system state
To meet the dynamic timing requirements of the memory system, any attempt to access
system state must occur synchronously with it. Therefore, ARM7TDM must be forced
to synchronize back to system speed. This is controlled by the 33rd bit of scan chain 1.
You can place any instruction in scan chain 1 with bit 33, the BREAKPT bit, LOW.
This instruction is then executed at debug speed. To execute an instruction at system
speed, the instruction prior to it must be scanned into scan chain 1 with bit 33 set HIGH.
After the system speed instruction has been scanned into the data bus and clocked into
the pipeline, the BYPASS instruction must be loaded into the TAP controller. This
makes the ARM7TDM automatically synchronize back to
MCLK,
the system clock,
executes the instruction at system speed, and then re-enters debug state and switches
itself back to the internally generated
DCLK
. When the instruction has completed,
DBGACK
is HIGH and the core switches back to
DCLK
. At this point, INTEST can
be selected in the TAP controller, and debugging can resume.
To determine that a system speed instruction has completed, the debugger must look at
both
DBGACK
and
nMREQ
. In order to access memory, ARM7TDM drives
nMREQ
LOW after it has synchronized back to system speed. This transition is used by the
memory controller to arbitrate whether ARM7TDM can have the bus in the next cycle.
If the bus is not available, ARM7TDM can have its clock stalled indefinitely.
Therefore, the only way to tell that the memory access has completed, is to examine the
state of both
nMREQ
and
DBGACK
. When both are HIGH, the access has completed.
The debugger normally uses EmbeddedICE Logic to control debugging, and by reading
the EmbeddedICE Logic status register, the state of
nMREQ
and
DBGACK
can be
determined. Refer to Chapter 8
EmbeddedICE Logic
for more details.
Using system speed load multiples and debug speed store multiples, the system memory
state can be fed back to the debug host.
Restrictions
There are restrictions on which instructions can have the 33rd bit set. The only valid
instructions where this bit can be set are:
loads
stores
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