
ARM DDI 0192A
Copyright ARM Limited 1997, 1998, 2000. All rights reserved.
vii
List of Tables
ARM720T
Technical Reference Manual
Table 1-1
Table 1-2
Table 1-3
Table 1-4
Table 1-5
Table 1-6
Table 1-7
Table 1-8
Table 1-9
Table 1-10
Table 1-11
Table 1-12
Table 2-1
Table 2-2
Table 2-3
Table 2-4
Table 3-1
Table 3-2
Table 3-3
Table 6-1
Table 6-2
Table 6-3
Table 6-4
Key to tables .........................................................................................1-5
ARM instruction summary.....................................................................1-8
Addressing mode 2.............................................................................1-11
Addressing mode 2 (privileged) ..........................................................1-12
Addressing mode 3.............................................................................1-12
Addressing mode 4 (load)...................................................................1-13
Addressing mode 4 (store)..................................................................1-13
Addressing mode 5.............................................................................1-14
Operand 2...........................................................................................1-14
Fields...................................................................................................1-14
Condition fields....................................................................................1-15
Thumb instruction summary ...............................................................1-17
ARM720T modes of operation..............................................................2-7
PSR mode bit values...........................................................................2-14
Exception entry and exit......................................................................2-17
Exception vector addresses................................................................2-20
Cache and MMU control register ..........................................................3-4
Cache operation....................................................................................3-9
TLB operations....................................................................................3-10
MMU program accessible registers.......................................................6-4
Interpreting level 1 descriptor bits [1:0].................................................6-7
Interpreting access permission (AP) bits.............................................6-10
Interpreting page table entry bits 1:0...................................................6-12