
ARM DDI 0192A
Copyright ARM Limited 1997, 1998, 2000. All rights reserved.
v
7.9
7.10
7.11
7.12
7.13
Determining the core and system state.......................................................7-25
The PC during debug..................................................................................7-30
Priorities and exceptions.............................................................................7-34
Scan interface timing ..................................................................................7-35
Scan and debug signals used by the embedded trace logic.......................7-42
Chapter 8
EmbeddedICE Logic
8.1
About EmbeddedICE Logic...........................................................................8-2
8.2
The watchpoint registers...............................................................................8-4
8.3
Programming breakpoints.............................................................................8-9
8.4
Programming watchpoints...........................................................................8-11
8.5
The debug control register..........................................................................8-13
8.6
Debug status register..................................................................................8-15
8.7
Coupling breakpoints and watchpoints .......................................................8-17
8.8
Debug communications channel.................................................................8-19
Chapter 9
Bus Clocking
9.1
9.2
9.3
About the ARM720T bus interface................................................................9-2
Fastbus extension.........................................................................................9-3
Standard mode .............................................................................................9-5
Chapter 10
AMBA Interface
10.1
About the AMBA interface...........................................................................10-2
10.2
ASB bus interface signals...........................................................................10-3
10.3
Cycle types .................................................................................................10-4
10.4
Addressing signals......................................................................................10-7
10.5
Memory request signals..............................................................................10-8
10.6
Data signal timing .......................................................................................10-9
10.7
Slave response signals.............................................................................10-10
10.8
Maximum sequential length ......................................................................10-12
10.9
Read-lock-write.........................................................................................10-13
10.10
Little-endian and big-endian operation......................................................10-14
10.11
Multi-master operation ..............................................................................10-17
10.12
Bus master handover................................................................................10-19
10.13
Default bus master....................................................................................10-21
Chapter 11
AMBA Test
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Slave operation, test mode .........................................................................11-2
ARM720T test mode...................................................................................11-3
ARM7TDM core test mode..........................................................................11-5
RAM test mode ...........................................................................................11-6
TAG test mode............................................................................................11-8
MMU test mode.........................................................................................11-10
Test register mapping ...............................................................................11-11
Chapter 12
Trace Interface Port
12.1
About the ETM............................................................................................12-2