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參數資料
| 型號： | L64007 |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數： | 114/166頁 |
| 文件大小： | 1015K |
| 代理商： | L64007 |
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Arch
43 Wed May 28 17:36:23 1997
Draft 1/21/97
L64007 MPEG-2, DVB, JSAT Transport Demultiplexer Technical Manual
2-43
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
Cyclic buffer 32 is devoted to storing transport adaptation elds of the
selected PIDs only. One byte of header information carrying the PID
Index is added to the beginning of each adaptation eld.
The MMU supports data transfer operations through the host processor
interface port. It provides a transfer service to the host DMA buffer and
the host Cache buffer. The host DMA buffer is serviced when the TR_EN
bit (in the DMA Transfer Control Register) is set to one. If it is a DMA
read or write operation, the direction is determined by the TR_DIR bit in
the control register. The address location in the DRAM memory is pro-
grammed in the DMA Pointer Register. Internally, a temporary DMA
Address Register is incremented by one with every DMA memory cycle.
The DMA cycle is terminated by resetting the TR_EN bit. The host
Cache buffer is serviced when the host processor tries a DMA read from
the external DRAM. In principle, each time the Cache controller logic sig-
nals a cache miss, a page of data is transferred from the DRAM memory
to the host Cache buffer. The page location is determined by the address
lines of the host processor.
2.4.5
Cache
Operation
The on-chip Cache is a high-speed, two-way associative memory. Each
Cache line contains eight words. For each of these it is possible to
access the high byte, the low byte, or the entire word. The Cache holds
the most frequently accessed data of larger and slower off-chip memory.
There are ve cache operation modes, which can be programmed by the
host processor:
Normal. In this mode, the host processor uses the Cache as a fast
buffer for the off-chip DRAM. If a cache read miss occurs, the miss-
ing word is the rst word fetched from DRAM and immediately deliv-
ered to the host processor.
Flush. In this mode, the contents of the host-processor-specied
address and the rest of the words in the same Cache line and set
are written back to the DRAM. An even host address selects set
zero, an odd host address selects set one.
Invalidate. In this mode, the host processor can invalidate the spec-
ied address and the Cache line containing that address. An even
host address selects set zero, an odd host address selects set one.
TAG direct. In this mode, the user can access TAG and control data
in the Cache. The host processor can use this mode to initialize the
Cache after the power-on reset or before it accesses the Cache. An
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