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參數資料
型號: L64007
廠商: LSI CORP
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝: PLASTIC, QFP-160
文件頁數: 146/166頁
文件大小: 1015K
代理商: L64007
Draft 1/16/97
3-8
Signal Denitions
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
CDERR
Channel Data Error
Input
This active LOW input signal indicates that an uncorrect-
able channel error occurred. It invokes error handling in
the L64007 transport chip.
CDRDY
Channel Data Ready
Output
This active HIGH output signal indicates that the channel
decoder is ready to accept new data. When this signal is
deasserted, it indicates that the channel decoder inter-
face is almost full, and any attempt to latch new data can
result in data loss.
CDSYNC
Channel Data Sync Start
Input
This active HIGH input signal indicates that there are
more than 10 slots on the channel decoder interface
FIFO. The use of this pin is a programmable option, since
the L64007 includes special logic that implements the
sync lock/unlock algorithm.
3.7
VCxO Master
Clock Interface
MCLK_SDC
Master Clock Sigma-Delta Control Voltage
Output
This 12-bit Sigma-Delta converter output is drives a sim-
ple low-pass lter to produce an analog control voltage to
an external VCXO.
3.8
Audio Clock
Interface
AVDD
Analog Power
Input
This input provides power to the audio clock generator’s
analog circuit. It must be isolated from the digital VDD by
ferrite with a value of 10
H.
AVSS
Analog Ground
Input
This input provides the analog ground to the audio clock
generator circuit. It must be isolated from the digital
ground supply (the implementation of this isolation is vari-
able).
IREF
Current Reference
Input
This signal interfaces to the external current source cir-
cuit, as shown in Figure 2.57 on page page 2-62.
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