
register
40 Wed May 28 17:37:25 1997
Draft 1/21/97
4-40
Registers
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
PPINT
PID Processor Interrupt
5
When this bit is set to 1, an interrupt was generated from
the PPU. The PSQ stores the status ags for this inter-
rupt. This bit is reset to 0 after a read from this register.
MMUINT
Memory Management Unit Interrupt
4
When this bit is set to 1, an interrupt was generated by
the MMU, indicating that a section of PSI data was
posted to the DRAM and is ready for the host to read.
This bit is reset to 0 after the read from this register.
PCR_INT
Program Clock Reference Interrupt
3
When this bit is set to 1, an interrupt was generated as a
result of latching a new transmitted PCR value carried by
the PCR_PID transport packet in the PCR. This also
latches the LMC Register with the value of the local clock
counter. This bit is reset to 0 after a read from this regis-
ter.
CHD_INT
Channel Decoder Interrupt
2
When this bit is set to 1, the channel decoder interface
logic has generated an interrupt, indicating that the event
status latched in the CSR is ready for the host to read.
This bit will be reset back to 0 after a read from this reg-
ister. After reset, this bit is reset to 0.
PSQ_CNT
PID Status Queue (PSQ) Counter
[1:0]
These two bits determine the number of pending status
words in the PSQ. Unlike other bits, this eld is not
affected by the read from the SSR; it is affected by the
read from the PSQ and the internal PID status write oper-
ation. To prevent an overow of the PSQ, it is recom-
mended that the host read the entire PSQ when it is
servicing the PP_INT ag. It is also recommended that
before returning from the interrupt service routine to the
PSQ CNT value, the PP_INT ag should be read again
to ensure there are no more status words pending. The
eld is 00 after RESET. When PSDQ_VAL = 0, the value
of PSQ_CNT is ignored and the PSQ FIFO is empty.