
register
46 Wed May 28 17:37:25 1997
Draft 1/21/97
4-46
Registers
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
Read operations to AMRF for which R > 4 (undened) are acknowl-
edged and return an unpredictable value in one of the real registers.
Write operations with N = 30 or 31 (undened) are acknowledged,
but no actual writes occur.
Read operations with N = 30 or 31 are acknowledged and return an
unpredictable value in one of the real registers.
4.10.1
Start Address
Register (SAR)
The read/write SAR determines the start address location of the cyclic
buffer for this PID. Internally, the SAR is a 20-bit address pointer register.
The SAR_MSB value lets users specify only the 16 MSBs of the 20-bit
address. The 4 LSBs are forced to zero on every write to this register.
This dictates a 16-word resolution per bit.
SAR_MSB
Start Address Register 16 MSBs
[15:0]
The specied value determines the start address location
of the cyclic buffer for this PID.
4.10.2
End Address
Register (EAR)
The read/write EAR determines the end address location of the cyclic
buffer for this PID. Internally, the EAR is a 20-bit address pointer register.
The EAR_MSB value lets user specify only the 16 MSBs of the 20-bit
address. The 4 LSBs are forced to 11112 on every write to this register.
For proper operation, the specied EAR_MSB value must be great than,
or equal to, the specied SAR_MSB value.
15
0
SAR_MSB
SAR_MSB
Start Address Location
0x0000
0
0x0001
16
0x0002
32
.
N
16*N
.
0xFFFF
16*65535 = 1048560