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19 Wed May 28 17:37:25 1997
Draft 1/21/97
L64007 MPEG-2, DVB, JSAT Transport Demultiplexer Technical Manual
4-19
PRE.4 for Rev. D
Copyright 1997 by LSI Logic Corporation. All rights reserved.
The implementation of this is shown in
Figure 2.8. The exact value pro-
grammed into this SDM register for a center frequency of 27MHz
depends on the VCx0 loop lter circuit. For the circuit shown in
Figure 2.7, a value of 0x9140 gives an approximate frequency of 27MHz.
4.7.2
Program Clock
Reference PID
(PCR_PID)
This is a 13-bit, read/write register that stores the PID value of the trans-
port packet carrying the PCRs of the program being decoded. When the
PCR_PID value matches the value of the PID in the transport packet
(assuming the PCR value is transmitted in this packet), the L64007
extracts the packet’s PCR value and stores it in the PCR registers (PLW,
PMW, and PHW, described below).
After reset, the value in this register is 0.
RES
Reserved
[15:13]
These bits are reserved.
PCR_PID
Program Clock Reference PID
[12:0]
This 13-bit eld stores the PID value of the transport
packet carrying the PCRs of the program being decoded.
4.7.3
Program Clock
Reference
(PCR) Register
The PCR comprises the PCR Low Word (PLW), PCR Middle Word
(PMW), and PCR High Word (PHW) registers, and six reserved bits. The
PCR value is a total of 42 bits. This PCR value is stored in three regis-
ters: PLW, PMW, and PHW.
.
0xFFFC
3 pulses every 64K clocks
0xFFFD
2 pulses every 64K clocks
0xFFFE
1 pulse every 64K clocks
0xFFFF
No pulses; output is HIGH
15
13
12
0
RES
PCR_PID
47
42 41
32 31
16 15
9 8
0
RES
PHW
PMW
PLW