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參數(shù)資料
型號： MC68B912B32FU8
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-Bit Microcontroller
中文描述： 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁數(shù)： 102/128頁
文件大小： 748K
代理商： MC68B912B32FU8
MOTOROLA
102
MC68HC912B32
MC68HC912B32TS/D
Figure 25 Types of In-Frame Response
TSIFR — Transmit Single Byte IFR with No CRC (Type 1 and Type 2)
Used to request the BDLC to transmit the byte in the BDLC data register (BDR) as a single byte IFR
with no CRC.
0 = TSIFR will be cleared automatically once the BDLC has successfully transmitted the byte in the
BDR onto the bus, or TEOD is set by the CPU, or an error is detected on the bus.
1 = If set prior to a valid EOD being received with no CRC error, once the EOD symbol has been
received the BDLC will attempt to transmit the appropriate normalization bit followed by the byte
in the BDR.
TMIFR0 — Transmit Multiple Byte IFR without CRC (Type 3)
Used to request the BDLC to transmit the byte in the BDLC data register (BDR) as the first byte of a
multiple byte IFR without CRC.
0 = TMIFR0 will be cleared automatically once the BDLC has successfully transmitted the EOD
symbol, by the detection of an error on the multiplex bus, or by a transmitter underrun caused
when the programmer does not write another byte to the BDR following the TDRE interrupt.
1 = If this bit is set prior to a valid EOD being received with no CRC error, once the EOD symbol
has been received the BDLC will attempt to transmit the appropriate normalization bit followed
by IFR bytes. The programmer should set TEOD after the last IFR byte has been written into
BDR register. After TEOD has been set, the last IFR byte to be transmitted will be the last byte
which was written into the BDR register.
TMIFR1 — Transmit Multiple Byte IFR with CRC (Type 3)
This bit requests the BDLC to transmit the byte in the BDLC data register (BDR) as the first byte of a
multiple byte IFR with CRC or as a single byte IFR with CRC.
0 = TMIFR1 will be cleared automatically once the BDLC has successfully transmitted the CRC byte
and EOD symbol, by the detection of an error on the multiplex bus, or by a transmitter underrun
caused when another byte is not written to the BDR following the TDRE interrupt.
1 = If set prior to a valid EOD being received with no CRC error, once the EOD symbol has been
received the BDLC will attempt to transmit the appropriate normalization bit followed by IFR
bytes. After TEOD has been set by software and the last IFR byte has been transmitted, the
CRC byte is transmitted.
NB
DATA FIELD
HEADER
CRC
DATA FIELD
DATA FIELD
DATA FIELD
HEADER
HEADER
HEADER
S
CRC
CRC
CRC
IFR DATA FIELD
E
CRC
S
S
S
E
E
E
E
E
E
NB
ID1
IDn
E
E
NB
ID
TYPE 0 — NO IFR
TYPE 1 — SINGLE BYTE FROM A SINGLE RESPONDER
TYPE 2 — SINGLE BYTE FROM MULTIPLE RESPONDERS
TYPE 3 — MULTIPLE BYTES FROM A SINGLE RESPONDER
E
E
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