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參數(shù)資料
| 型號： | MC68B912B32FU8 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-Bit Microcontroller |
| 中文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 14/128頁 |
| 文件大小： | 748K |
| 代理商： | MC68B912B32FU8 |
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MOTOROLA
14
MC68HC912B32
MC68HC912B32TS/D
Table 5 MC68HC912B32 Signal Description Summary
Pin Name
PW[3:0]
ADDR[7:0]
DATA[7:0]
ADDR[15:8]
DATA[15:8]
Pin Number
3–6
Description
Pulse Width Modulator channel outputs.
25–18
External bus pins share function with general-purpose I/O ports A and B. In sin-
gle chip modes, the pins can be used for I/O. In expanded modes, the pins are
used for the external buses.
46–39
IOC[7:0]
16–12, 9–7
Pins used for input capture and output compare in the timer and pulse accumu-
lator subsystem.
Pulse accumulator input
Analog inputs for the analog-to-digital conversion module
Data bus control and, in expanded mode, enables the drive control of external
buses during external reads.
State of mode select pins during reset determine the initial operating mode of the
MCU. After reset, MODB and MODA can be configured as instruction queue
tracking signals IPIPE1 and IPIPE0 or as general-purpose I/O pins.
E-clock is the output connection for the external bus clock. ECLK is used as a
timing reference and for address demultiplexing.
An active low bidirectional control signal, RESET acts as an input to initialize the
MCU to a known start-up state, and an output when COP or clock monitor causes
a reset.
PAI
16
AN[7:0]
58–51
DBE
26
MODB, MODA
27, 28
IPIPE1, IPIPE0
27, 28
ECLK
29
RESET
32
EXTAL
XTAL
33
34
Crystal driver and external clock input pins. On reset all the device clocks are de-
rived from the EXTAL input frequency. XTAL is the crystal output.
LSTRB
35
Low byte strobe (0 = low byte valid), in all modes this pin can be used as I/O. The
low strobe function is the exclusive-NOR of A0 and the internal SZ8 signal. (The
SZ8 internal signal indicates the size 16/8 access.)
Pin used in instruction tagging. See
16 Development Support
.
Indicates direction of data on expansion bus. Shares function with general-pur-
pose I/O. Read/write in expanded modes.
Maskable interrupt request input provides a means of applying asynchronous in-
terrupt requests to the MCU. Either falling edge-sensitive triggering or level-sen-
sitive triggering is program selectable (INTCR register).
Provides a means of requesting asynchronous non-maskable interrupt
requests
after reset initialization.
Single-wire background interface pin is dedicated to the background debug func-
tion. During reset, this pin determines special or normal operating mode.
Pin used in instruction tagging. See
16 Development Support
.
BDLC receive pin
BDLC transmit pin
Slave select output for SPI master mode, input for slave mode or master mode.
Serial clock for SPI system.
Master out/slave in pin for serial peripheral interface
Master in/slave out pin for serial peripheral interface
SCI transmit pin
SCI receive pin
TAGLO
35
R/W
36
IRQ
37
XIRQ
38
BKGD
17
TAGHI
DLCRx
DLCTx
CS/SS
SCK
SDO/MOSI
SDI/MISO
TxD0
RxD0
17
76
75
68
67
66
65
62
61
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