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參數(shù)資料
| 型號(hào)： | MC68B912B32FU8 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-Bit Microcontroller |
| 中文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 106/128頁 |
| 文件大小： | 748K |
| 代理商： | MC68B912B32FU8 |
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MOTOROLA
106
MC68HC912B32
MC68HC912B32TS/D
Read and write anytime.
DDDLC[6:0] — Data Direction Port DLC Pin 6 through Pin 0
0 = Configure I/O pin for input only
1 = Configure I/O pin for output
14.5 J1850 Bus Errors
The BDLC detects several types of transmit and receive errors which can occur during the transmission
of a message onto the J1850 bus.
If the BDLC transmits a message containing invalid bits, or framing symbols on non-byte boundaries,
then a transmission error has occurred. When a transmission error is detected, the BDLC will immedi-
ately cease transmitting. The error condition is reflected in the BSVR register. If the interrupt enable bit
(IE) is set, an interrupt request from the BDLC is generated.
CRC Error
— A CRC error is detected when the data bytes and CRC byte of a received message are
processed, and the CRC calculation result is not equal to $C4. The CRC code should detect any single
and 2-bit errors, as well as all 8-bit burst errors, and almost all other types of errors. CRC error flag is
set when a CRC error is detected.
Symbol Error
— A symbol error is detected when an abnormal (invalid) symbol is detected in a mes-
sage being received from the J1850 bus. However, if the BDLC is transmitting when this happens, it
may be treated as a loss of arbitration rather than a transmitter error. Symbol invalid or out of range flag
is set when a symbol error is detected.
Framing Error
— A framing error is detected if an EOD or EOF symbol is detected on a non-byte
boundary from the J1850 bus. Symbol invalid or out of range flag is set when a framing error is detected.
Bus Fault
— If a bus fault occurs, the response of the BDLC will depend upon the type of bus fault.
If the bus is shorted to V
BATT
, the BDLC will wait for the bus to fall to a passive state before it will attempt
to transmit a message. As long as the short remains, the BDLC will never attempt to transmit a message
onto the J1850 bus.
If the bus is shorted to ground, the BDLC will see an idle bus, begin to transmit the message, and then
detect a transmission error, since the short to ground would not allow the bus to be driven to the active
(dominant) state. The BDLC will abort that transmission and wait for the next CPU command to transmit.
In any case, if the bus fault is temporary, as soon as the fault is cleared, the BDLC will resume normal
operation. If the bus fault is permanent, it may result in permanent loss of communication on the J1850
bus.
BREAK
— Any BDLC transmitting at the time a BREAK is detected will treat the BREAK as if a trans-
mission error had occurred, and halt transmission.
If while receiving a message the BDLC detects a BREAK symbol, it will treat the BREAK as a reception
error.
DDRDLC
— Port DLC Data Direction Register
$00FF
Bit 7
6
5
4
3
2
1
Bit 0
0
DDDLC6
DDDLC5
DDDLC4
DDDLC3
DDDLC2
DDDLC1
DDDLC0
RESET:
0
0
0
0
0
0
0
0
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