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參數(shù)資料
| 型號(hào)： | MC68B912B32FU8 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-Bit Microcontroller |
| 中文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁(yè)數(shù)： | 114/128頁(yè) |
| 文件大小： | 748K |
| 代理商： | MC68B912B32FU8 |
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MOTOROLA
114
MC68HC912B32
MC68HC912B32TS/D
RST — Module Reset Bit
When set, this bit causes all registers and activity in the module to assume the same state as out of
power-on reset (except for ADPU bit in ATDCTL2, which remains set, allowing the ATD module to re-
main enabled).
TSTOUT — Multiplex Output of TST[3:0] (Factory Use)
TST[3:0] — Test Bits 3 to 0 (Reserved)
Selects one of 16 reserved factory testing modes.
PAD[7:0] — Port AD Data Input Bits
After reset these bits reflect the state of the input pins.
May be used for general-purpose digital input. When the software reads PORTAD, it obtains the digital
levels that appear on the corresponding port AD pins. Pins with signals not meeting V
IL
or V
IH
specifi-
cations will have an indeterminate value. Writes to this register have no meaning at any time.
ADRxH[7:0] — ATD Conversion Result
The reset condition for these registers is undefined.
These bits contain the left justified, unsigned result from the ATD conversion. The channel from which
this result was obtained is dependent on the conversion mode selected. These registers are always
read-only in normal mode.
15.3 ATD Mode Operation
STOP — causes all clocks to halt (if the S bit in the CCR is zero). The system is placed in a minimum-
power standby mode. This aborts any conversion sequence in progress. During STOP recovery, the
ATD must delay for the STOP recovery time (t
SR
) before initiating a new ATD conversion sequence.
WAIT — ATD conversion continues unless AWAI bit in ATDCTL2 register is set.
BDM — Debug options available as set in register ATDCTL3.
USER — ATD continues running unless ADPU is cleared.
ADPU — ATD operations are stopped if ADPU = 0, but registers are accessible.
PORTAD —
Port AD Data Input Register
$006F
Bit 7
6
5
4
3
2
1
Bit 0
PAD7
PAD6
PAD5
PAD4
PAD3
PAD2
PAD1
PAD0
RESET:
–
–
–
–
–
–
–
–
ADR0H —
ATD Converter Result Register 0
ADR1H —
ATD Converter Result Register 1
ADR2H —
ATD Converter Result Register 2
ADR3H —
ATD Converter Result Register 3
ADR4H —
ATD Converter Result Register 4
ADR5H —
ATD Converter Result Register 5
ADR6H —
ATD Converter Result Register 6
ADR7H —
ATD Converter Result Register 7
$0070
$0072
$0074
$0076
$0078
$007A
$007C
$007E
$007x
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
RESET:
–
–
–
–
–
–
–
–
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