- 您現在的位置：買賣IC網 > PDF目錄371046 > MC68B912B32FU8 (MOTOROLA INC) 16-Bit Microcontroller PDF資料下載
參數資料
| 型號： | MC68B912B32FU8 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-Bit Microcontroller |
| 中文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數： | 98/128頁 |
| 文件大小： | 748K |
| 代理商： | MC68B912B32FU8 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁當前第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁
MOTOROLA
98
MC68HC912B32
MC68HC912B32TS/D
14 Byte Data Link Communications Module (BDLC)
The byte data link communications module (BDLC) provides access to an external serial communica-
tion multiplex bus, operating according to the SAE J1850 protocol.
14.1 Features
Features of the BDLC module include the following:
SAE J1850 compatible
10.4 Kbps VPW bit format
Digital noise filter
Collision detection
Hardware CRC generation and checking
Two power saving modes with automatic wake up on network activity
Polling and CPU interrupts with vector lookup available
Receive and transmit block mode supported
Supports 4X receive mode (41.6 Kbps)
Digital loopback mode
In-frame response (IFR) types 0, 1, 2, and 3 supported
Dedicated register for symbol timing adjustments
Digital module only, requires external analog transceiver
NOTE
It is recommended that the reader be familiar with the SAE Standard J1850 Class
B Data Communication Network Interfacespecification prior to proceeding with this
section.
14.2 BDLC Operating Modes
The BDLC has five main modes of operation which interact with the power supplies, pins and the MCU.
Power Off
is entered from the reset mode whenever the BDLC supply voltage V
DD
drops below the min-
imum value for guaranteed operation. In this mode, the pin input and output specifications are not guar-
anteed.
Reset
is entered from the power off mode whenever the BDLC supply voltage V
DD
rises above its min-
imum specified value and an MCU reset source is asserted. To prevent the BDLC from entering an un-
known state, the internal MCU reset is asserted while powering up the BDLC. In reset mode, the internal
BDLC voltage references are operative, V
DD
is supplied to the internal circuits, which are held in their
reset state and the internal BDLC system clock is running. Registers will assume their reset condition.
Outputs are held in their programmed reset state. Inputs and network activity are ignored.
Run
is entered from the reset mode after all MCU reset sources are no longer asserted. It is entered
from the BDLC wait mode whenever activity is sensed on the J1850 bus. Run mode is entered from the
BDLC stop mode whenever network activity is sensed though messages will not be received properly
until the clocks have stabilized and the CPU is also in the run mode. In run mode, normal network op-
eration takes place. Ensure that all BDLC transmissions cease before exiting this mode.
BDLC Wait
power-conserving mode is automatically entered from the run mode whenever the CPU ex-
ecutes a WAIT instruction and if the WCM bit in the BCR register has been cleared. In this mode, the
BDLC internal clocks continue to run. The first passive-to-active transition of the bus wakes up the
BDLC and the CPU. If a valid byte is successfully received a CPU interrupt request will be generated.
BDLC Stop
power-conserving mode is automatically entered from the run mode whenever the CPU
executes a STOP instruction, or if the CPU executes a WAIT instruction and the WCM bit in the BCR
register has been set. In this mode, the BDLC internal clocks are stopped until network activity is sensed
and a CPU interrupt request is generated.
相關PDF資料 |
PDF描述 |
|---|---|
| MC68C912B32CFU8 | 16-Bit Microcontroller |
| MC68CK338 | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| MC68EC060 | 32-Bit Microprocessors.(32位微處理器) |
| MC68EN360RC25V | QUad Integrated Communications Controller Users Manual |
| MC68EN360CFE25 | QUad Integrated Communications Controller Users Manual |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MC68BOOL | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:8-BIT MICROPROCESSING UNIT (MPU) |
| MC68BOOP | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:8-BIT MICROPROCESSING UNIT (MPU) |
| MC68BOOS | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:8-BIT MICROPROCESSING UNIT (MPU) |
| MC68C812A4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Technical Supplement MC68C812A4 3.3V Electrical Characteristics |
| MC68C912B32CFU8 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:16-Bit Microcontroller |
發布緊急采購，3分鐘左右您將得到回復。