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參數資料
| 型號： | MC68B912B32FU8 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-Bit Microcontroller |
| 中文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數： | 118/128頁 |
| 文件大小： | 748K |
| 代理商： | MC68B912B32FU8 |
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MOTOROLA
118
MC68HC912B32
MC68HC912B32TS/D
Figure 29 BDM Target to Host Serial Bit Timing (Logic 0)
Figure 29
shows the host receiving a logic zero from the target MC68HC912B32 MCU. Since the host
is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge
on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but
the target MC68HC912B32 finishes it. Since the target wants the host to receive a logic zero, it drives
the BKGD pin low for 13 E-clock cycles, then briefly drives it high to speed up the rising edge. The host
samples the bit level about ten cycles after starting the bit time.
16.2.3 BDM Commands
All BDM command opcodes are eight bits long, and can be followed by an address and/or data, as in-
dicated by the instruction. These commands do not require the CPU to be in active BDM mode for ex-
ecution.
The host controller must wait 150 cycles for a non-intrusive BDM command to execute before another
command can be sent. This delay includes 128 cycles for the maximum delay for a dead cycle. For data
read commands, the host must insert this delay between sending the address and attempting to read
the data.
BDM logic retains control of the internal buses until a read or write is completed. If an operation can be
completed in a single cycle, it does not intrude on normal CPU operation. However, if an operation re-
quires multiple cycles, CPU clocks are frozen until the operation is complete.
10 CYCLES
E CLOCK
(TARGET
MCU)
EARLIEST
START OF
NEXT BIT
BKGD PIN
PERCEIVED
START OF BIT TIME
10 CYCLES
HOST SAMPLES
BKGD PIN
HOST
DRIVE TO
BKGD PIN
TARGET MCU
DRIVE AND
SPEEDUP PULSE
HIGH-IMPEDANCE
SPEEDUP PULSE
HC12A4 BDM TARGET TO HOST TIM 0
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