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參數資料
| 型號： | MC68B912B32FU8 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-Bit Microcontroller |
| 中文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數： | 89/128頁 |
| 文件大小： | 748K |
| 代理商： | MC68B912B32FU8 |
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MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
89
NF — Noise Error Flag
Set during the same cycle as the RDRF bit but not set in the case of an overrun (OR).
0 = Unanimous decision
1 = Noise on a valid start bit, any of the data bits, or on the stop bit
FE — Framing Error Flag
Set when a zero is detected where a stop bit was expected. Clear the FE flag by reading SC0SR1 with
FE set and then reading SC0DR.
0 = Stop bit detected
1 = Zero detected rather than a stop bit
PF — Parity Error Flag
Indicates if received data’s parity matches parity bit. This feature is active only when parity is enabled.
The type of parity tested for is determined by the PT (parity type) bit in SC0CR1.
0 = Parity correct
1 = Incorrect parity detected
Read anytime. Write has no meaning or effect.
RAF — Receiver Active Flag
This bit is controlled by the receiver front end. It is set during the RT1 time period of the start bit search.
It is cleared when an idle state is detected or when the receiver circuitry detects a false start bit (gener-
ally due to noise or baud rate mismatch).
0 = A character is not being received
1 = A character is being received
R8 — Receive Bit 8
Read anytime. Write has no meaning or affect.
This bit is the ninth serial data bit received when the SCI system is configured for nine-data-bit opera-
tion.
T8 — Transmit Bit 8
Read or write anytime.
This bit is the ninth serial data bit transmitted when the SCI system is configured for nine-data-bit oper-
ation. When using 9-bit data format this bit does not have to be written for each data word. The same
value will be transmitted as the ninth bit until this bit is rewritten.
SC0SR2
— SCI Status Register 2
$00C5
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
RAF
RESET:
0
0
0
0
0
0
0
0
SC0DRH
— SCI Data Register High
$00C6
Bit 7
6
5
4
3
2
1
Bit 0
R8
T8
0
0
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
SC0DRL
— SCI Data Register Low
$00C7
Bit 7
6
5
4
3
2
1
Bit 0
R7/T7
R6/T6
R5/T5
R4/T4
R3/T3
R2/T2
R1/T1
R0/T0
RESET:
0
0
0
0
0
0
0
0
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