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| 型號： | MPC750 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Hall Effect Switch IC; Package/Case:3-SOT-23; Supply Voltage Max:24V; Current Rating:4mA; Leaded Process Compatible:Yes; Operate Point Max:90G; Operate Point Min:-90G; Operational Type:Latch; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| 中文描述： | MPC750 RISC微處理器 |
| 文件頁數： | 10/31頁 |
| 文件大小： | 318K |
| 代理商： | MPC750 |
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10
MPC750 RISC Microprocessor Technical Summary
For More Information On This Product,
Go to: www.freescale.com
1.1.3 Memory Management Units (MMUs)
The MPC750’s MMUs support up to 4 Petabytes (2
memory for instructions and data. The MMUs also control access privileges for these spaces on block and
page granularities. Referenced and changed status is maintained by the processor for each page to support
demand-paged virtual memory systems.
52
) of virtual memory and 4 Gigabytes (2
32
) of physical
The LSU calculates effective addresses for data loads and stores; the instruction unit calculates effective
addresses for instruction fetching. The MMU translates the effective address to determine the correct
physical address for the memory access.
The MPC750 supports the following types of memory translation:
Real addressing mode—In this mode, translation is disabled by clearing bits in the machine state
register (MSR): MSR[IR] for instruction fetching or MSR[DR] for data accesses. When address
translation is disabled, the physical address is identical to the effective address.
Page address translation—translates the page frame address for a 4-Kbyte page size
Block address translation—translates the base address for blocks (128 Kbytes to 256 Mbytes)
If translation is enabled, the appropriate MMU translates the higher-order bits of the effective address into
physical address bits. The lower-order address bits (that are untranslated and therefore, considered both
logical and physical) are directed to the on-chip caches where they form the index into the eight-way set-
associative tag array. After translating the address, the MMU passes the higher-order physical address bits
to the cache and the cache lookup completes. For caching-inhibited accesses or accesses that miss in the
cache, the untranslated lower-order address bits are concatenated with the translated higher-order address
bits; the resulting 32-bit physical address is used by the memory unit and the system interface, which
accesses external memory.
The TLBs store page address translations for recent memory accesses. For each access, an effective address
is presented for page and block translation simultaneously. If a translation is found in both the TLB and the
BAT array, the block address translation in the BAT array is used. Usually the translation is in a TLB and
the physical address is readily available to the on-chip cache. When a page address translation is not in a
TLB, hardware searches for one in the page table following the model defined by the PowerPC architecture.
Instruction and data TLBs provide address translation in parallel with the on-chip cache access, incurring
no additional time penalty in the event of a TLB hit. The MPC750’s TLBs are 128-entry, two-way set-
associative caches that contain instruction and data address translations. The MPC750 automatically
generates a TLB search on a TLB miss.
1.1.4 On-Chip Instruction and Data Caches
The MPC750 implements separate instruction and data caches. Each cache is 32-Kbyte and eight-way set
associative. As defined by the PowerPC architecture, they are physically indexed. Each cache block contains
eight contiguous words from memory that are loaded from an 8-word boundary (that is, bits EA[27–31] are
zeros); thus, a cache block never crosses a page boundary. An entire cache block can be updated by a four-
beat burst load. Misaligned accesses across a page boundary can incur a performance penalty. Caches are
nonblocking, write-back caches with hardware support for reloading on cache misses. The critical double
word is transferred on the first beat and is simultaneously written to the cache and forwarded to the
requesting unit, minimizing stalls due to load delays. The cache being loaded is not blocked to internal
accesses while the load completes.
The MPC750 cache organization is shown in Figure 2.
F
Freescale Semiconductor, Inc.
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.
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