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| 型號： | MPC750 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Hall Effect Switch IC; Package/Case:3-SOT-23; Supply Voltage Max:24V; Current Rating:4mA; Leaded Process Compatible:Yes; Operate Point Max:90G; Operate Point Min:-90G; Operational Type:Latch; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| 中文描述： | MPC750 RISC微處理器 |
| 文件頁數： | 27/31頁 |
| 文件大小： | 318K |
| 代理商： | MPC750 |
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MPC750 RISC Microprocessor Technical Summary
27
The hashed page table is a variable-sized data structure that defines the mapping between virtual page
numbers and physical page numbers. The page table size is a power of 2, and its starting address is a multiple
of its size. The page table contains a number of page table entry groups (PTEGs). A PTEG contains eight
page table entries (PTEs) of eight bytes each; therefore, each PTEG is 64 bytes long. PTEG addresses are
entry points for table search operations.
Setting MSR[IR] enables instruction address translations and MSR[DR] enables data address translations.
If the bit is cleared, the respective effective address is the same as the physical address.
2.5.2 MPC750 Memory Management Implementation
The MPC750 implements separate MMUs for instructions and data. It implements a copy of the segment
registers in the instruction MMU, however, read and write accesses (
mfsr
and
mtsr
) are handled through
the segment registers implemented as part of the data MMU. The MPC750 MMU is described in
Section 1.1.3, “Memory Management Units (MMUs).”
The R (referenced) bit is updated in the PTE in memory (if necessary) during a table search due to a TLB
miss. Updates to the C (changed) bit are treated like TLB misses. A complete table search is performed and
the entire TLB entry is rewritten to update the C bit.
2.6 Instruction Timing
The MPC750 is a pipelined, superscalar processor. A pipelined processor is one in which instruction
processing is divided into discrete stages, allowing work to be done on different instructions in each stage.
For example, after an instruction completes one stage, it can pass on to the next stage leaving the previous
stage available to the subsequent instruction. This improves overall instruction throughput.
A superscalar processor is one that issues multiple independent instructions into separate execution units,
allowing instructions to execute in parallel. The MPC750 has six independent execution units, two for
integer instructions, and one each for floating-point instructions, branch instructions, load/store instructions,
and system register instructions. Having separate GPRs and FPRs allows integer, floating-point calculations,
and load and store operations to occur simultaneously without interference. Additionally, rename buffers are
provided to allow operations to post execution results for use by subsequent instructions without committing
them to the architected FPRs and GPRs.
As shown in Figure 6, the common pipeline of the MPC750 has four stages through which all instructions
must pass—fetch, decode/dispatch, execute, and complete/write back. Some instructions occupy multiple
stages simultaneously and some individual execution units have additional stages. For example, the floating-
point pipeline consists of three stages through which all floating-point instructions must pass.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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