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| 型號： | MPC750 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Hall Effect Switch IC; Package/Case:3-SOT-23; Supply Voltage Max:24V; Current Rating:4mA; Leaded Process Compatible:Yes; Operate Point Max:90G; Operate Point Min:-90G; Operational Type:Latch; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| 中文描述： | MPC750 RISC微處理器 |
| 文件頁數： | 11/31頁 |
| 文件大小： | 318K |
| 代理商： | MPC750 |
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MPC750 RISC Microprocessor Technical Summary
11
Figure 2. Cache Organization
Within one cycle, the data cache provides double-word access to the LSU. Like the instruction cache, the
data cache can be invalidated all at once or on a per-cache-block basis. The data cache can be disabled and
invalidated by clearing HID0[DCE] and setting HID0[DCFI]. The data cache can be locked by setting
HID0[DLOCK]. To ensure cache coherency, the data cache supports the three-state MEI protocol. The data
cache tags are single-ported, so a simultaneous load or store and a snoop access represent a resource
collision. If a snoop hit occurs, the LSU is blocked internally for one cycle to allow the eight-word block of
data to be copied to the write-back buffer.
Within one cycle, the instruction cache provides up to four instructions to the instruction queue. The
instruction cache can be invalidated entirely or on a cache-block basis. The instruction cache can be disabled
and invalidated by clearing HID0[ICE] and setting HID0[ICFI]. The instruction cache can be locked by
setting HID0[ILOCK]. The instruction cache supports only the valid/invalid states.
The MPC750 also implements a 64-entry (16-set, four-way set-associative) branch target instruction cache
(BTIC). The BTIC is a cache of branch instructions that have been encountered in branch/loop code
sequences. If the target instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than
it can be made available from the instruction cache. Typically the BTIC contains the first two instructions
in the target stream. The BTIC can be disabled and invalidated through software. For more information, see
Section 1.1.2.2, “Branch Processing Unit (BPU).”
1.1.5 L2 Cache Implementation (Not Supported in the MPC740)
The L2 cache is a unified cache that receives memory requests from both the L1 instruction and data caches
independently. The L2 cache is implemented with an on-chip, two-way, set-associative tag memory, and
with external, synchronous SRAMs for data storage. The external SRAMs are accessed through a dedicated
L2 cache port that supports a single bank of up to 1 Mbyte of synchronous SRAMs. The L2 cache normally
operates in write-back mode and supports system cache coherency through snooping.
8 Words/Block
128 Sets
Block 5
Block 6
Block 7
Block 4
Address Tag 4
Address Tag 5
Address Tag 6
Address Tag 7
Block 1
Block 2
Block 3
Block 0
Address Tag 0
Address Tag 1
Address Tag 2
Address Tag 3
State
State
State
Words [0–7]
State
Words [0–7]
Words [0–7]
Words [0–7]
State
State
State
Words [0–7]
State
Words [0–7]
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F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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