- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382345 > MPC750 (Motorola, Inc.) Hall Effect Switch IC; Package/Case:3-SOT-23; Supply Voltage Max:24V; Current Rating:4mA; Leaded Process Compatible:Yes; Operate Point Max:90G; Operate Point Min:-90G; Operational Type:Latch; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes PDF資料下載
參數(shù)資料
| 型號： | MPC750 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Hall Effect Switch IC; Package/Case:3-SOT-23; Supply Voltage Max:24V; Current Rating:4mA; Leaded Process Compatible:Yes; Operate Point Max:90G; Operate Point Min:-90G; Operational Type:Latch; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| 中文描述： | MPC750 RISC微處理器 |
| 文件頁數(shù)： | 12/31頁 |
| 文件大小： | 318K |
| 代理商： | MPC750 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
12
MPC750 RISC Microprocessor Technical Summary
For More Information On This Product,
Go to: www.freescale.com
Depending on its size, the L2 cache is organized into 64- or 128-byte lines, which in turn are subdivided
into 32-byte sectors (blocks), the unit at which cache coherency is maintained.
The L2 cache controller contains the L2 cache control register (L2CR), which includes bits for enabling
parity checking, setting the L2-to-processor clock ratio, and identifying the type of RAM used for the L2
cache implementation. The L2 cache controller also manages the L2 cache tag array, two-way set-
associative with 4K tags per way. Each sector (32-byte cache block) has its own valid and modified status
bits.
Requests from the L1 cache generally result from instruction misses, data load or store misses, write-
through operations, or cache management instructions. Requests from the L1 cache are looked up in the L2
tags and serviced by the L2 cache if they hit; they are forwarded to the bus interface if they miss.
The L2 cache can accept multiple, simultaneous accesses. The L1 instruction cache can request an
instruction at the same time that the L1 data cache is requesting one load and two store operations. The L2
cache also services snoop requests from the bus. If there are multiple pending requests to the L2 cache,
snoop requests have highest priority. The next priority consists of load and store requests from the L1 data
cache. The next priority consists of instruction fetch requests from the L1 instruction cache.
1.1.6 System Interface/Bus Interface Unit (BIU)
The address and data buses operate independently; address and data tenures of a memory access are
decoupled to provide a more flexible control of memory traffic. The primary activity of the system interface
is transferring data and instructions between the processor and system memory. There are two types of
memory accesses:
Single-beat transfers—These memory accesses allow transfer sizes of 8, 16, 24, 32, or 64 bits in
one bus clock cycle. Single-beat transactions are caused by uncacheable read and write operations
that access memory directly (that is, when caching is disabled), cache-inhibited accesses, and stores
in write-through mode.
Four-beat burst (32 bytes) data transfers—Burst transactions, which always transfer an entire cache
block (32 bytes), are initiated when an entire cache block is transferred. Because the first-level
caches on the MPC750 are write-back caches, burst-read memory, burst operations are the most
common memory accesses, followed by burst-write memory operations, and single-beat
(noncacheable or write-through) memory read and write operations.
The MPC750 also supports address-only operations, variants of the burst and single-beat operations, (for
example, atomic memory operations and global memory operations that are snooped), and address retry
activity (for example, when a snooped read access hits a modified block in the cache). The broadcast of some
address-only operations is controlled through HID0[ABE]. I/O accesses use the same protocol as memory
accesses.
Access to the system interface is granted through an external arbitration mechanism that allows devices to
compete for bus mastership. This arbitration mechanism is flexible, allowing the MPC750 to be integrated
into systems that implement various fairness and bus parking procedures to avoid arbitration overhead.
Typically, memory accesses are weakly ordered—sequences of operations, including load/store string and
multiple instructions, do not necessarily complete in the order they begin—maximizing the efficiency of the
bus without sacrificing data coherency. The MPC750 allows read operations to go ahead of store operations
(except when a dependency exists, or in cases where a noncacheable access is performed), and provides
support for a write operation to go ahead of a previously-queued read data tenure (for example, letting a
snoop push be enveloped between address and data tenures of a read operation). Because the MPC750 can
dynamically optimize run-time ordering of load/store traffic, overall performance is improved.
F
Freescale Semiconductor, Inc.
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC823 | Communication Processor Module |
| MPC823UM_REV1_16-CPM7 | 10 AMP SUBMINIATURE POWER RELAY |
| MPC9109 | LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP |
| MPC9229 | 400 MHz Low Voltage PECL Clock Synthesizer |
| MPC9230 | 800 MHz Low Voltage PECL Clock Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC75-103J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Metal Plate Cement Resistors |
| MPC75-103K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Metal Plate Cement Resistors |
| MPC75201J | 功能描述:厚膜電阻器 - 透孔 MPC7 200R 5% RoHS:否 制造商:Caddock 電阻:27 kOhms 容差:1 % 功率額定值:8 W 溫度系數(shù):50 PPM / C 系列:MS 端接類型:Axial 電壓額定值:2 kV 工作溫度范圍:- 15 C to + 275 C 尺寸:8.89 mm Dia. x 23.11 mm L 封裝:Bulk |
| MPC755 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:RISC Microprocessor Hardware Specifications |
| MPC755BPX300LE | 功能描述:微處理器 - MPU 360PBGA RV2.8 HIP4DP RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。