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| 型號： | MPC750 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Hall Effect Switch IC; Package/Case:3-SOT-23; Supply Voltage Max:24V; Current Rating:4mA; Leaded Process Compatible:Yes; Operate Point Max:90G; Operate Point Min:-90G; Operational Type:Latch; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| 中文描述： | MPC750 RISC微處理器 |
| 文件頁數： | 28/31頁 |
| 文件大小： | 318K |
| 代理商： | MPC750 |
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MPC750 RISC Microprocessor Technical Summary
For More Information On This Product,
Go to: www.freescale.com
Figure 6. Pipeline Diagram
Note that Figure 6 does not show features, such as reservation stations and rename buffers that reduce stalls
and improve instruction throughput.
The instruction pipeline in the MPC750 has four major pipeline stages, described as follows:
The fetch pipeline stage primarily involves retrieving instructions from the memory system and
determining the location of the next instruction fetch. The BPU decodes branches during the fetch
stage and removes those that do not update CTR or LR from the instruction stream.
The dispatch stage is responsible for decoding the instructions supplied by the instruction fetch
stage and determining which instructions can be dispatched in the current cycle. If source operands
for the instruction are available, they are read from the appropriate register file or rename register
to the execute pipeline stage. If a source operand is not available, dispatch provides a tag that
indicates which rename register will supply the operand when it becomes available. At the end of
the dispatch stage, the dispatched instructions and their operands are latched by the appropriate
execution unit.
Instructions executed by the IUs, FPU, SRU, and LSU are dispatched from the bottom two positions
in the instruction queue. In a single clock cycle, a maximum of two instructions can be dispatched
to these execution units in any combination. When an instruction is dispatched, it is assigned a
position in the six-entry completion queue. A branch instruction can be issued on the same clock
cycle for a maximum three-instruction dispatch.
During the execute pipeline stage, each execution unit that has an executable instruction executes
the selected instruction (perhaps over multiple cycles), writes the instruction's result into the
appropriate rename register, and notifies the completion stage that the instruction has finished
execution. In the case of an internal exception, the execution unit reports the exception to the
completion pipeline stage and (except for the FPU) discontinues instruction execution until the
exception is handled. The exception is not signaled until that instruction is the next to be completed.
Execution of most floating-point instructions is pipelined within the FPU allowing up to three
instructions to be executing in the FPU concurrently. The FPU stages are multiply, add, and round-
Fetch
Complete (Write Back)
Dispatch
Execute Stage
FPU3
SRU
IU1
IU2
Maximum three-instruction dispatch per
clock cycle (includes one branch
instruction)
Maximum two-instruction completion
per clock cycle
FPU2
FPU1
LSU1
Maximum four-instruction fetch per
clock cycle
LSU2
BPU
F
Freescale Semiconductor, Inc.
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