
MPC750 RISC Microprocessor Technical Summary
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convert. Execution of most load/store instructions is also pipelined. The load/store unit has two
pipeline stages. The first stage is for effective address calculation and MMU translation and the
second stage is for accessing the data in the cache.
The complete pipeline stage maintains the correct architectural machine state and transfers
execution results from the rename registers to the GPRs and FPRs (and CTR and LR, for some
instructions) as instructions are retired. As with dispatching instructions from the instruction queue,
instructions are retired from the two bottom positions in the completion queue. If completion logic
detects an instruction causing an exception, all following instructions are cancelled, their execution
results in rename registers are discarded, and instructions are fetched from the appropriate
exception vector.
Because the PowerPC architecture can be applied to such a wide variety of implementations, instruction
timing varies among PowerPC processors.
2.7 Power Management
The MPC750 provides four power modes, selectable by setting the appropriate control bits in the MSR and
HID0 registers. The four power modes are as follows:
Full-power—This is the default power state of the MPC750. The MPC750 is fully powered and the
internal functional units are operating at the full processor clock speed. If the dynamic power
management mode is enabled, functional units that are idle will automatically enter a low-power
state without affecting performance, software execution, or external hardware.
Doze—All the functional units of the MPC750 are disabled except for the time base/decrementer
registers and the bus snooping logic. When the processor is in doze mode, an external asynchronous
interrupt, a system management interrupt, a decrementer exception, a hard or soft reset, or machine
check brings the MPC750 into the full-power state. The MPC750 in doze mode maintains the PLL
in a fully powered state and locked to the system external clock input (SYSCLK) so a transition to
the full-power state takes only a few processor clock cycles.
Nap—The nap mode further reduces power consumption by disabling bus snooping, leaving only
the time base register and the PLL in a powered state. The MPC750 returns to the full-power state
upon receipt of an external asynchronous interrupt, a system management interrupt, a decrementer
exception, a hard or soft reset, or a machine check input (MCP). A return to full-power state from
a nap state takes only a few processor clock cycles. When the processor is in nap mode, if QACK
is negated, the processor is put in doze mode to support snooping.
Sleep—Sleep mode minimizes power consumption by disabling all internal functional units, after
which external system logic may disable the PLL and SYSCLK. Returning the MPC750 to the full-
power state requires the enabling of the PLL and SYSCLK, followed by the assertion of an external
asynchronous interrupt, a system management interrupt, a hard or soft reset, or a machine check
input (MCP) signal after the time required to relock the PLL.
2.8 Thermal Management
The MPC750’s thermal assist unit (TAU) provides a way to control heat dissipation. This ability is
particularly useful in portable computers, which, due to power consumption and size limitations, cannot use
desktop cooling solutions such as fans. Therefore, better heat sink designs coupled with intelligent thermal
management is of critical importance for high performance portable systems.
Primarily, the thermal management system monitors and regulates the system’s operating temperature. For
example, if the temperature is about to exceed a set limit, the system can be made to slow down or even
suspend operations temporarily in order to lower the temperature.
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Freescale Semiconductor, Inc.
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