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參數(shù)資料
| 型號(hào)： | MPC750 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Hall Effect Switch IC; Package/Case:3-SOT-23; Supply Voltage Max:24V; Current Rating:4mA; Leaded Process Compatible:Yes; Operate Point Max:90G; Operate Point Min:-90G; Operational Type:Latch; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| 中文描述： | MPC750 RISC微處理器 |
| 文件頁數(shù)： | 25/31頁 |
| 文件大小： | 318K |
| 代理商： | MPC750 |
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MPC750 RISC Microprocessor Technical Summary
25
2.4.2 MPC750 Exception Implementation
The MPC750 exception classes described above are shown in Table 4.
Although exceptions have other characteristics, such as priority and recoverability, Table 4 describes
categories of exceptions the MPC750 handles uniquely. Table 4 includes no synchronous imprecise
exceptions; although the PowerPC architecture supports imprecise handling of floating-point exceptions,
the MPC750 implements these exception modes precisely. Table 5 lists MPC750 exceptions and conditions
that cause them. Exceptions specific to the MPC750 are indicated.
Table 4. MPC750 Microprocessor Exception Classifications
Synchronous/Asynchronous Precise/Imprecise
Exception Type
Asynchronous, nonmaskable
Imprecise
Machine check, system reset
Asynchronous, maskable
Precise
External, decrementer, system management, performance
monitor, and thermal management interrupts
Synchronous
Precise
Instruction-caused exceptions
Table 5. Exceptions and Conditions
Exception Type
Vector Offset
(hex)
Causing Conditions
Reserved
00000
—
System reset
00100
Assertion of either HRESET or SRESET or at power-on reset
Machine check
00200
Assertion of TEA during a data bus transaction, assertion of MCP, or an
address, data, or L2 bus parity error. MSR[ME] must be set.
DSI
00300
As specified in the PowerPC architecture. For TLB misses on load, store, or
cache operations, a DSI exception occurs if a page fault occurs.
ISI
00400
As defined by the PowerPC architecture.
External interrupt
00500
MSR[EE] = 1 and INT is asserted.
Alignment
00600
A floating-point load/store,
stmw
,
stwcx.
,
lmw
,
lwarx
,
eciwx
or
ecowx
instruction operand is not word-aligned.
A multiple/string load/store operation is attempted in little-endian mode.
The operand of
dcbz
is in memory that is write-through-required or
caching-inhibited or the cache is disabled
Program
00700
As defined by the PowerPC architecture.
Floating-point
unavailable
00800
As defined by the PowerPC architecture.
Decrementer
00900
As defined by the PowerPC architecture, when the most-significant bit of the
DEC register changes from 0 to 1 and MSR[EE] = 1.
Reserved
00A00–00BFF —
System call
00C00
Execution of the System Call (
sc
) instruction.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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