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| 型號： | MPC750 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Hall Effect Switch IC; Package/Case:3-SOT-23; Supply Voltage Max:24V; Current Rating:4mA; Leaded Process Compatible:Yes; Operate Point Max:90G; Operate Point Min:-90G; Operational Type:Latch; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| 中文描述： | MPC750 RISC微處理器 |
| 文件頁數： | 13/31頁 |
| 文件大小： | 318K |
| 代理商： | MPC750 |
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MPC750 RISC Microprocessor Technical Summary
13
The system interface is specific for each PowerPC microprocessor implementation.
The MPC750 signals are grouped as shown in Figure 3. Signals are provided for clocking and control of the
L2 caches, as well as separate L2 address and data buses. Test and control signals provide diagnostics for
selected internal circuits.
Figure 3. System Interface
The system interface supports address pipelining, which allows the address tenure of one transaction to
overlap the data tenure of another. The extent of the pipelining depends on external arbitration and control
circuitry. Similarly, the MPC750 supports split-bus transactions for systems with multiple potential bus
masters—one device can have mastership of the address bus while another has mastership of the data bus.
Allowing multiple bus transactions to occur simultaneously increases the available bus bandwidth for other
activity.
The MPC750’s clocking structure supports a wide range processor-to-bus clock ratios.
1.1.7 Signals
The MPC750’s signals are grouped as follows:
Address arbitration signals—The MPC750 uses these signals to arbitrate for address bus
mastership.
Address start signals—These signals indicate that a bus master has begun a transaction on the
address bus.
Address transfer signals—These signals include the address bus and address parity signals. They
are used to transfer the address and to ensure the integrity of the transfer.
Transfer attribute signals—These signals provide information about the type of transfer, such as the
transfer size and whether the transaction is bursted, write-through, or caching-inhibited.
Address termination signals—These signals are used to acknowledge the end of the address phase
of the transaction. They also indicate whether a condition exists that requires the address phase to
be repeated.
Data arbitration signals—The MPC750 uses these signals to arbitrate for data bus mastership.
Data transfer signals—These signals, which consist of the data bus and data parity signals, are used
to transfer the data and to ensure the integrity of the transfer.
Address Arbitration
Address Start
Address Transfer
Transfer Attribute
Address Termination
Clocks
Data Arbitration
Data Transfer
Data Termination
Processor Status/Control
Test and Control
L2 Cache Address/Data
1
L2 Cache Clock/Control
1
System Status
V
DD
V
DD
(I/O)
MPC750
1
Not supported in the MPC740
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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