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| 型號： | MPC750 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Hall Effect Switch IC; Package/Case:3-SOT-23; Supply Voltage Max:24V; Current Rating:4mA; Leaded Process Compatible:Yes; Operate Point Max:90G; Operate Point Min:-90G; Operational Type:Latch; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| 中文描述： | MPC750 RISC微處理器 |
| 文件頁數： | 2/31頁 |
| 文件大小： | 318K |
| 代理商： | MPC750 |
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MPC750 RISC Microprocessor Technical Summary
For More Information On This Product,
Go to: www.freescale.com
Part 1 MPC750 Microprocessor Overview
This section describes the features and general operation of the MPC750 and provides a block diagram
showing major functional units. The MPC750 is an implementation of the PowerPC microprocessor family
of reduced instruction set computer (RISC) microprocessors. The MPC750 implements the 32-bit portion
of the PowerPC architecture, which provides 32-bit effective addresses, integer data types of 8, 16, and 32
bits, and floating-point data types of 32 and 64 bits. The MPC750 is a superscalar processor that can
complete two instructions simultaneously. It incorporates the following six execution units:
Floating-point unit (FPU)
Branch processing unit (BPU)
System register unit (SRU)
Load/store unit (LSU)
Two integer units (IUs): IU1 executes all integer instructions. IU2 executes all integer instructions
except multiply and divide instructions.
The ability to execute several instructions in parallel and the use of simple instructions with rapid execution
times yield high efficiency and throughput for MPC750-based systems. Most integer instructions execute in
one clock cycle. The FPU is pipelined, the tasks it performs are broken into subtasks, implemented as three
successive stages. Typically, a floating-point instruction can occupy only one of the three stages at a time,
freeing the previous stage to work on the next floating-point instruction. Thus, three single-precision
floating-point instructions can be in the FPU execute stage at a time. Double-precision add instructions have
a three-cycle latency; double-precision multiply and multiply-add instructions have a four-cycle latency.
Figure 1 shows the parallel organization of the execution units (shaded in the diagram). The instruction unit
fetches, dispatches, and predicts branch instructions. Note that this is a conceptual model that shows basic
features rather than attempting to show how features are implemented physically.
The MPC750 has independent on-chip, 32-Kbyte, eight-way set-associative, physically addressed caches
for instructions and data and independent instruction and data memory management units (MMUs). Each
MMU has a 128-entry, two-way set-associative translation lookaside buffer (DTLB and ITLB) that saves
recently used page address translations. Block address translation is done through the four-entry instruction
and data block address translation (IBAT and DBAT) arrays, defined by the PowerPC architecture. During
block translation, effective addresses are compared simultaneously with all four BAT entries.
The L2 cache is implemented with an on-chip, two-way, set-associative tag memory, and with external,
synchronous SRAMs for data storage. The external SRAMs are accessed through a dedicated L2 cache port
that supports a single bank of up to 1 Mbyte of synchronous SRAMs. The L2 cache interface is not
implemented in the MPC740.
The MPC750 has a 32-bit address bus and a 64-bit data bus. Multiple devices compete for system resources
through a central external arbiter. The MPC750’s three-state cache-coherency protocol (MEI) supports the
exclusive, modified, and invalid states, a compatible subset of the MESI (modified/exclusive/shared/invalid)
four-state protocol, and it operates coherently in systems with four-state caches. The MPC750 supports
single-beat and burst data transfers for memory accesses and memory-mapped I/O operations.
The MPC750 has four software-controllable power-saving modes. Three static modes, doze, nap, and sleep,
progressively reduce power dissipation. When functional units are idle, a dynamic power management mode
causes those units to enter a low-power mode automatically without affecting operational performance,
software execution, or external hardware. The MPC750 also provides a thermal assist unit (TAU) and a way
to reduce the instruction fetch rate for limiting power dissipation.
The MPC750 uses an advanced CMOS process technology and is fully compatible with TTL devices.
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