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| 型號： | MPC750 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Hall Effect Switch IC; Package/Case:3-SOT-23; Supply Voltage Max:24V; Current Rating:4mA; Leaded Process Compatible:Yes; Operate Point Max:90G; Operate Point Min:-90G; Operational Type:Latch; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| 中文描述： | MPC750 RISC微處理器 |
| 文件頁數： | 26/31頁 |
| 文件大小： | 318K |
| 代理商： | MPC750 |
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26
MPC750 RISC Microprocessor Technical Summary
For More Information On This Product,
Go to: www.freescale.com
2.5 Memory Management
The following subsections describe the memory management features of the PowerPC architecture, and the
MPC750 implementation, respectively.
2.5.1 PowerPC Memory Management Model
The primary functions of the MMU are to translate logical (effective) addresses to physical addresses for
memory accesses and to provide access protection on blocks and pages of memory. There are two types of
accesses generated by the MPC750 that require address translation—instruction accesses, and data accesses
to memory generated by load, store, and cache control instructions.
The PowerPC architecture defines different resources for 32- and 64-bit processors; the MPC750
implements the 32-bit memory management model. The memory-management model provides 4 Gbytes of
logical address space accessible to supervisor and user programs with a 4-Kbyte page size and 256-Mbyte
segment size. BAT block sizes range from 128 Kbyte to 256 Mbyte and are software selectable. In addition,
it defines an interim 52-bit virtual address and hashed page tables for generating 32-bit physical addresses.
The architecture also provides independent four-entry BAT arrays for instructions and data that maintain
address translations for blocks of memory. These entries define blocks that can vary from 128 Kbytes to 256
Mbytes. The BAT arrays are maintained by system software.
The PowerPC MMU and exception model support demand-paged virtual memory. Virtual memory
management permits execution of programs larger than the size of physical memory; demand-paged implies
that individual pages are loaded into physical memory from system memory only when they are first
accessed by an executing program.
1
MPC750-specific
Trace
00D00
MSR[SE] = 1 or a branch instruction completes and MSR[BE] = 1. Unlike the
architecture definition,
isync
does not cause a trace exception.
Reserved
00E00
The MPC750 does not generate an exception to this vector. Other PowerPC
processors may use this vector for floating-point assist exceptions.
Reserved
00E10–00EFF —
Performance monitor
1
00F00
The limit specified in a PMC register is reached and MMCR0[ENINT] = 1.
Instruction address
breakpoint
1
01300
IABR[0–29] matches EA[0–29] of the next instruction to complete, IABR[TE]
matches MSR[IR], and IABR[BE] = 1.
System management
interrupt
1
01400
MSR[EE] = 1 and SMI is asserted.
Reserved
01500–016FF
—
Thermal management
interrupt
1
01700
Thermal management is enabled, the junction temperature exceeds the
threshold specified in THRM1 or THRM2, and MSR[EE] = 1.
Reserved
01800–02FFF
—
Table 5. Exceptions and Conditions (Continued)
Exception Type
Vector Offset
(hex)
Causing Conditions
F
Freescale Semiconductor, Inc.
n
.
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