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參數資料
| 型號： | MPC750 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Hall Effect Switch IC; Package/Case:3-SOT-23; Supply Voltage Max:24V; Current Rating:4mA; Leaded Process Compatible:Yes; Operate Point Max:90G; Operate Point Min:-90G; Operational Type:Latch; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| 中文描述： | MPC750 RISC微處理器 |
| 文件頁數： | 20/31頁 |
| 文件大小： | 318K |
| 代理商： | MPC750 |
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20
MPC750 RISC Microprocessor Technical Summary
For More Information On This Product,
Go to: www.freescale.com
Table 3 describes the SPRs in the MPC750 that are not defined by the PowerPC architecture.
DABR
Supervisor
The optional
data address breakpoint register (DABR) supports the data address
breakpoint facility.
DAR
User
The data address register (DAR) holds the address of an access after an alignment or DSI
exception.
DEC
Supervisor
The decrementer register (DEC) is a 32-bit decrementing counter that provides a way to
schedule decrementer exceptions.
DSISR
User
The DSISR defines the cause of data access and alignment exceptions.
EAR
Supervisor
The external access register (EAR) controls access to the external access facility through
the External Control In Word Indexed (
eciwx
) and External Control Out Word Indexed
(
ecowx
) instructions.
PVR
Supervisor
The processor version register (PVR) is a read-only register that identifies the processor.
SDR1
Supervisor
SDR1 specifies the page table format used in virtual-to-physical page address translation.
SRR0
Supervisor
The machine status save/restore register 0 (SRR0) saves the address used for restarting
an interrupted program when a Return from Interrupt (
rfi
) instruction executes.
SRR1
Supervisor
The machine status save/restore register 1 (SRR1) is used to save machine status on
exceptions and to restore machine status when an
rfi
instruction is executed.
SPRG0–
SPRG3
Supervisor
SPRG0–SPRG3 are provided for operating system use.
TB
User: read
Supervisor:
read/write
The time base register (TB) is a 64-bit register that maintains the time of day and operates
interval timers. The TB consists of two 32-bit fields—time base upper (TBU) and time base
lower (TBL).
XER
User
The XER contains the summary overflow bit, integer carry bit, overflow bit, and a field
specifying the number of bytes to be transferred by a Load String Word Indexed (
lswx
) or
Store String Word Indexed (
stswx
) instruction.
Table 3. MPC750-Specific Registers
Register
Level
Function
HID0
Supervisor The hardware implementation register 0 (HID0) provides checkstop enables and other
functions.
HID1
Supervisor The hardware implementation register 1 (HID1) allows software to read the configuration
of the PLL configuration signals.
IABR
Supervisor The instruction address breakpoint register (IABR) supports instruction address
breakpoint exceptions. It can hold an address to compare with instruction addresses in
the IQ. An address match causes an instruction address breakpoint exception.
ICTC
Supervisor The instruction cache-throttling control register (ICTC) has bits for controlling the interval
at which instructions are fetched into the instruction buffer in the instruction unit. This
helps control the MPC750’s overall junction temperature.
L2CR
Supervisor The L2 cache control register (L2CR) is used to configure and operate the L2 cache. It
has bits for enabling parity checking, setting the L2-to-processor clock ratio, and
identifying the type of RAM used for the L2 cache implementation. (The L2 cache feature
is not supported in the MPC740.)
Table 2. Architecture-Defined SPRs Implemented by the MPC750 (Continued)
Register
Level
Function
F
Freescale Semiconductor, Inc.
n
.
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