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| 型號： | MPC750 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Hall Effect Switch IC; Package/Case:3-SOT-23; Supply Voltage Max:24V; Current Rating:4mA; Leaded Process Compatible:Yes; Operate Point Max:90G; Operate Point Min:-90G; Operational Type:Latch; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| 中文描述： | MPC750 RISC微處理器 |
| 文件頁數： | 23/31頁 |
| 文件大小： | 318K |
| 代理商： | MPC750 |
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MPC750 RISC Microprocessor Technical Summary
23
2.2.2 MPC750 Instruction Set
The MPC750 instruction set is defined as follows:
The MPC750 provides hardware support for all 32-bit PowerPC instructions.
The MPC750 implements the following instructions optional to the PowerPC architecture:
— External Control In Word Indexed (
eciwx
)
— External Control Out Word Indexed
(
ecowx
)
— Floating Select (
fsel
)
— Floating Reciprocal Estimate Single-Precision (
fres
)
— Floating Reciprocal Square Root Estimate (
frsqrte
)
— Store Floating-Point as Integer Word (
stfiwx
)
2.3 On-Chip Cache Implementation
The following subsections describe the PowerPC architecture’s treatment of cache in general, and the
MPC750-specific implementation, respectively.
2.3.1 PowerPC Cache Model
The PowerPC architecture does not define hardware aspects of cache implementations. For example,
PowerPC processors can have unified caches, separate instruction and data caches (Harvard architecture),
or no cache at all. PowerPC microprocessors control the following memory access modes on a page or block
basis:
Write-back/write-through mode
Caching-inhibited mode
Memory coherency
The caches are physically addressed, and the data cache can operate in either write-back or write-through
mode as specified by the PowerPC architecture.
The PowerPC architecture defines the term ‘cache block’ as the cacheable unit. The VEA and OEA define
cache management instructions a programmer can use to affect cache contents.
2.3.2 MPC750 Cache Implementation
The MPC750 cache implementation is described in Section 1.1.4, “On-Chip Instruction and Data Caches,”
and Section 1.1.5, “L2 Cache Implementation (Not Supported in the MPC740).” The BPU also contains a
64-entry BTIC that provides immediate access to cached target instructions. For more information, see
Section 1.1.2.2, “Branch Processing Unit (BPU).”
2.4 Exception Model
The following sections describe the PowerPC exception model and the MPC750 implementation.
2.4.1 PowerPC Exception Model
The PowerPC exception mechanism allows the processor to interrupt the instruction flow to handle certain
situations caused by external signals, errors, or unusual conditions arising from the instruction execution.
When exceptions occur, information about the state of the processor is saved to certain registers and the
processor begins execution at an address (exception vector) predetermined for each exception. Exception
processing occurs in supervisor mode.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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