
1996 Oct 29
111
Philips Semiconductors
Objective specification
GSM signal processing IC
PCF5083
10.2
Interrupt Logic
The PCF5083 provides three active LOW interrupt lines:
FRAME_INT, COMB_INT and HIPR_INT for use with the
microcontroller. These interrupt lines are described in
Table 97.
Table 97
Interrupt lines
INTERRUPT
DESCRIPTION
FRAME_INT
This output generates an interrupt at the
beginning of every TDMA frame. The
interrupt is deactivated with an access to
register MODE0_REG.
This output combines three different
interrupts:
COMB_INT
HWCTRL_INT: indicates all interrupts
from the on/off monitor, MMI
power-down unit and the real time clock.
All these interrupt sources are encoded
in register HWCTRL_REG
IOM_INT: indicates all interrupts from
the IOM
-2 interface encoded in
registers IOMFLAG_REG and
IOMCTRL_REG. Enable flags for this
interrupt source are provided in register
IOMEN_REG.
SI_INT: indicates all interrupts from the
RF-IC bus interface and the RS232
interface encoded in register
SIINT_REG. Enable flags for this
interrupt source are provided in register
SIMASK_REG.
The register COMBINT_REG contains
an interrupt flag and an enable flag for
each of the three interrupts. The
interrupt flags are inactive if none of their
corresponding interrupt conditions is
active and enabled.
This outputs combines some high
priority interrupt sources derived from
the RF-IC bus trigger signals generated
from the timing generator, from the
TDMA frame interrupt and the host port
of the DSP core. The register
HIPRINT_REG holds flags for each
interrupt condition and the register
HIPRMASK_REG the corresponding
interrupt enable flags. For further details
refer to Section 10.1
HIPR_INT
11 RESET
The PCF5083 has three asynchronous, active LOW reset
inputs: RSTO, RSTC and RST.
RSTO resets the ON/OFF monitor. RSTC the real time
clock unit. For a proper reset, RSTO and RSTC have to be
asserted until the 32.768 kHz oscillator has stabilized.
RST controls all other parts of the PCF5083. RST is
connected to the system reset. For a proper reset, RST
has to be asserted for at least 62.5 ms.
After powering-up the PCF5083 all reset lines RSTO,
RSTC and RST must be asserted to achieve a defined
state of the IC.
The DSP core reset is driven via the general purpose
parallel port bit 0. After an external reset via RST, this port
pin is set to a logic 0. The DSP core is therefore set into
the reset state.
12 JTAG TEST INTERFACE
The PCF5083 JTAG interface is used to increase
testability at board level. The interface is implemented in
accordance with IEEE Std 1149.1-1990, IEEE Standard
Test Access Port and Boundary-Scan Architecture.
The interface signals are specified in Table 98 and the
operations supported by the interface are given in
Table 99.
Table 98
JTAG test interface signals
SIGNAL
DESCRIPTION
TRSTN
Test Reset, active LOW input. This signal
resets the internal TAP controller and the
state of the boundary-scan cells. It must be
pulled LOW during normal operation to
ensure that the boundary scan circuitry does
not influence the application logic.
Test Clock input.
Test Mode Select input. This signal controls
the internal state machine of the TAP
controller.
Test Data Input to shift in instructions and
data are applied to the boundary-scan
circuitry.
Test Data Out. While shifting in data at the
port TDI, data in also shifted out serially at
this pin. The instruction register and the data
registers are always connected between TDI
and TDO.
TCK
TMS
TDI
TDO