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參數資料
| 型號： | PCF5083 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | STEEL COVER |
| 中文描述： | GSM信號處理IC |
| 文件頁數： | 21/136頁 |
| 文件大小： | 602K |
| 代理商： | PCF5083 |
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1996 Oct 29
21
Philips Semiconductors
Objective specification
GSM signal processing IC
PCF5083
8.3.1
T
HE
Q
UARTERBIT
C
OUNTER
The quarterbit counter (QBC) represents the timebase of
the mobile. It consists of a 13-bit upcounter. The counter
directly counts the quarterbit steps within one TDMA
frame. Its range is therefore 0 to 4999.
At the beginning of every TDMA frame (quarterbit counter
state 0) the signal FRAME_INT goes LOW, generating an
interrupt (frame interrupt) to the System Controller. The
interrupt line is deactivated by accessing the register
MODE0_REG. The frame interrupt is disabled with
MODEx_REG[DISFRAMEINT] = 1.
8.3.1.1
Initial Quarterbit Counter Timing Alignment
The timing offset between a base station and a mobile
station can be corrected by presetting the quarterbit
counter with an estimated correction value. Therefore the
register QBC_REG has to be set up with this correction
value in frame N and the flag QBRCTRL_REG[SYNC] has
to be set.
At the end of frame N the quarterbit counter is loaded from
QBC_REG with zeros. The duration of frame N + 1 is
5000
[QBC_REG] and the mobile will be synchronised at
the beginning of frame N + 2. The frame interrupt at the
beginning of frame N + 1 is disabled. The timing
generation is disabled during frame N + 1. The SYNC flag
is cleared after synchronization.
For the System Controller the resulting timing looks like
frame N being extended and synchronization being
achieved with frame N + 1.
8.3.1.2
Maintaining the Quarterbit Counter Timing
Alignment
Small timing corrections can be made by inserting or
extracting one quarterbit step at the beginning of a TDMA
frame. Therefore the INSERT or EXTRACT flag in register
QBCCTRL_REG have to be set. These flags are cleared
after the timing alignment was performed.
8.3.2
N
ORMAL MODE
In Normal mode the Timing Generator provides the output
signals specified in Table 8.
The power-down signals NPDTX2, NPDTX1 and
NPDBIAS are active LOW by default. All other signals are
active HIGH by default. Active HIGH in this context means
that the signals are on high level during a receive or a
transmit burst.
The output polarity can be changed by setting the
corresponding bit in register POL_REG to a logic 1. The
signals can be clamped to a level depending on their flag
in POL_REG by setting the corresponding bit in register
MASK_REG to a logic 0.
After a reset with RST, the receiver, transmitter and
synthesizer control lines are set to their inactive level.
The general MS timing is assumed to have the receive
timeslot (RX) in timeslot 0, the transmit timeslot (TX) in
timeslot 3 and the monitor timeslot (MON) in timeslot 6
within a TDMA frame.
Table 8
Output signals
SIGNAL
DESCRIPTION
Signals for the receiver section
RXON
BEN
PDRX1
PDRX2
baseband interface IC receiver enable
baseband interface IC enable
receiver power-down 1
receiver power-down 2
Signals for the transmitter section
TXON
BEN
TXKEY1
TXKEY2
PDTX1
NPDTX1
NPDTX2
PDPIAS
NPDBIAS
baseband interface IC transmitter enable
baseband interface IC enable
power amplifier power-down
power ramping controller trigger signal
transmitter power-down 1
inverted output of PDTX1
transmitter power-down 2
power amplifier bias voltage power-down
inverted output of PDBIAS
Signal for the synthesizer
PDSYN
synthesizer power-down
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PCF5083H/001/F2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC |
| PCF5083H/5V2/F3 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC |
| PCF5083H/F2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC |
| PCF51AC128ACFUE | 功能描述:32位微控制器 - MCU 32 Bit 128K FLASH 32K RAM CAN EN RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數據總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數據 RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT |
| PCF51AC128ACLKE | 功能描述:32位微控制器 - MCU 32 Bit 128K FLASH 32K RAM CAN EN RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數據總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數據 RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT |
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