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參數資料
| 型號： | PCF5083 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | STEEL COVER |
| 中文描述： | GSM信號處理IC |
| 文件頁數： | 39/136頁 |
| 文件大小： | 602K |
| 代理商： | PCF5083 |
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1996 Oct 29
39
Philips Semiconductors
Objective specification
GSM signal processing IC
PCF5083
8.5.2
IOM
-2 M
ASTER
U
NIT
The IOM
-2 master unit implements two monitor channels
and C/I channel masters. All handshake protocols are
implemented in accordance with the IOM
-2 standard with
the exception of the constraints mentioned below. The
data structure of a 16-bit monitor and C/I timeslot is also
implemented according to the IOM
-2 standard with the
exception that the timeslot location is not fixed within a
IOM
-2 frame.
As data is structured in 16-bit timeslots (see Table 24) the
timeslot a master works on, can be selected with the flags
IOMCON_REG[MASTERx_TS0 to MASTERx_TS3].
These bits binary encode the timeslot number (0 to 5), with
timeslot 0 being indicated with the rising edge of FSC.
Both monitor masters can be independently enabled with
the flags IOMCON_REG[MASTERx_EN].
For every serviced channel a data register (MON0_REG,
MON1_REG, CI0_REG and CI1_REG) with input and
output buffer stage and a state machine for receive and
transmit direction exists. For every register
IOMFLAG_REG holds two flags to indicate the input data
buffer full and the output buffer empty condition. The flags
are xxx_IBF (input buffer full) and xxx_OBE (output buffer
empty) with xxx equal to the register name. If one of these
flags together with the corresponding enable flag in
IOMEN_REG is set the IOM
-2 interrupt is activated (refer
to Section 10.2). The flags are reset with read respectively
write operations to their corresponding data register.
8.5.3
M
ONITOR
C
HANNEL
T
RANSMITTER
P
ROTOCOL
After IOMCON_REG[MASTERx_EN] is set to a logic 1,
the transmitter state machine is in an idle state. The
pattern FFH is sent and the output buffer empty flag
MONx_OBE (x = 1 or 2) is set. The MX flag is sent as a
logic 1 in accordance with the IOM
-2 specifications.
To initiate a message transmission the System
Controller has to program MONx_REG with the first byte
of the message. The MONx_OBE flag is cleared with the
data write access.
A full handshake is implemented in accordance with the
IOM
-2 specifications. The transmitter may delay the
data transmission in case the System Controller does
not provide new data in time. MX = 0 is maintained until
MONx_REG is programmed with new data. The
MONx_OBE flag is cleared with the data write access.
The receiver delays the data transmission if it sends no
data acknowledge. In this case MX = 0 is maintained
and the data byte is repeated in subsequent frames.
To request new data from the controller the MONx_OBE
flag may be set as soon as the data acknowledge
(MR = 1) from the receiver is detected except for the first
byte reception. Here the MR transition HIGH-to-LOW
has to be detected. This leaves the controller
approximately 250
μ
s to program the MONx_REG with
the next byte without delay within the handshake
procedure except for the first byte.
An end of transmission is sent if the TEOMx flag in
IOMCTRL_REG is set when MONx_OBE = 1 after the
last byte transmission. The end of transmission is sent
(MX = 1 in at least two subsequent frames) after the
acknowledge of the last byte is completely received.
After the end of transmission is sent the transmitter state
machine is in the idle state.
The TEOMx flags are also used to initialize the
transmitter state machine. If the flag is set the state
machine may get from any state into the idle state.
The TEOMx flag is automatically cleared.
If an abort request is received, the transmitter in
accordance with the specifications, sends the end of
transmission sequence and enters the idle state. The
MONx_OBE flag is set. The abort request is indicated
with the RABORTx flag set in IOMCTRL_REG.
RABORTx = 1 also asserts the IOM
-2 interrupt
(MONx_OBE_EN is used as enable bit) to indicate the
abort to the System Controller. The flag is reset with the
MONx_OBE flag.
Table 24
Data structure of a 16-bit IOM
-2 monitor and C/I master timeslot
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MONX
C/IX
MR
MX
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PCF5083H/001/F2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC |
| PCF5083H/5V2/F3 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC |
| PCF5083H/F2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC |
| PCF51AC128ACFUE | 功能描述:32位微控制器 - MCU 32 Bit 128K FLASH 32K RAM CAN EN RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數據總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數據 RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT |
| PCF51AC128ACLKE | 功能描述:32位微控制器 - MCU 32 Bit 128K FLASH 32K RAM CAN EN RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數據總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數據 RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT |
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