- 您現在的位置：買賣IC網 > PDF目錄382382 > PCF5083 (NXP Semiconductors N.V.) STEEL COVER PDF資料下載
參數資料
| 型號： | PCF5083 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | STEEL COVER |
| 中文描述： | GSM信號處理IC |
| 文件頁數： | 41/136頁 |
| 文件大小： | 602K |
| 代理商： | PCF5083 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁當前第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁
1996 Oct 29
41
Philips Semiconductors
Objective specification
GSM signal processing IC
PCF5083
8.5.8
E
XTERNAL
IOM
-2 I
NTERFACE
This block provides an IOM
-2 interface for external
devices and accessories e.g. digital handsfree equipment
data and fax interfaces etc. It is used as an interface to the
system simulator during type approval.
The external IOM
-2 interface (DCL, FSC, DU and DD) is
only enabled if the flag IOMCON_REG[IOMEXT_EN] is
set. Otherwise, unless in external clock mode, the outputs
DCL, FSC and DD are in their high-impedance state and
the input DU is don’t care (default after reset). In external
clock mode the flag IOMCON_REG[IOMEXT_EN] flag
only controls the data lines DU and DD. DCL and FSC are
inputs in this mode independently from the state of the flag.
If the flag IOMCON_REG[IOMEXT_INV] is set, all I/Os of
the external IOM
-2 interface are inverted to allow the use
of an external inverting driver circuit.
If the external IOM
-2 interface is disabled with
IOMCON_REG[IOMEXT_EN] = 0, the DU input is
externally pulled-up and will be monitored for a LOW level.
An external device has to pull-down this line to register
itself. If a LOW on DU was detected, the SI_INT interrupt
is activated with flag SIINT_REG[EXT_IOM] set. The flag
and therefore the interrupt condition is automatically
cleared after IOMCON_REG[IOMEXT_EN] was set.
8.6
MMI Interface
The PCF5083 provides a RS232 and a Power-down
interface to fully support the MMI controller TDA8005.
8.6.1
RS232 I
NTERFACE
This block provides a full RS232 interface with a fixed
8E1 protocol configuration.
The shift clock is derived from the 1 MHz clock for normal
operation. For test purposes a clock applied at input ADI is
used if SYSCON_REG[RS232_CLK] is set. The clock is
divided by 12
×
3
×
16 to derive the shift clock. This results
in a baud rate of 22569.44 Baud at 13 MHz. The receiver
works with an oversampling of 16.
8.6.1.1
Transmit
After writing to the register TXD_REG, the register content
is serially clocked out. The SIINT_REG[TXD_OBE] flag is
set and the SI_INT interrupt is generated (refer to
Section 10.2). The flag and therefore the interrupt
condition is cleared after writing the next data byte to
register TXD_REG.
8.6.1.2
Receive
The incoming serial data stream is clocked into register
RXD_REG. SIINT_REG[RXD_IBF] is set after a data byte
was received and the SI_INT interrupt is generated. The
state of the RXD_IBF flag is available on the MMIEN
output and is used to implement a hardware handshake to
the TDA8005. The SIINT_REG[PAR_ERR] flag signals a
parity error and will be updated when the RXD_IBF flag
goes active. The RXD_IBF flag and therefore the interrupt
condition is cleared automatically after reading the register
RXD_REG.
Both interrupt conditions can be disabled with the
corresponding mask flags in SIMASK_REG. The flag
handling remains the same as described.
The output MMIEN is set to a logic 1 as long as
HWCTRL_REG[MMICLK] = 0.
Note that PAR_ERR is not used as an interrupt condition.
8.6.2
MMI
POWER
-
DOWN INTERFACE
The MMI power-down interface controls the power
consumption of the MMI controller (MMIC) TDA8005 by
halting its main 13 MHz clock. The following signals are
used:
MMICLK: 13 MHz clock output, main clock for the MMIC
MMIREQ: MMI clock request input.
The MMI wake-up and power-down procedures are:
1.
Force MMIC into power-down mode:
Set HWCTRL_REG[MMICLK] = 0 to stop the 13 MHz
MMI clock. The MMICLK output is held LOW and the
output MMIEN of the RS232 interface is set HIGH.
2.
Wake-up MMIC via System Controller:
Set HWCTRL_REG[MMICLK] = 1 to activate
MMICLK.
3.
Wake-up MMIC after keyboard or SIM card reader
activity:
In this case the MMIC generates a LOW-to-HIGH
transition on pin MMIREQ. The flags MMIREQ and
MMICLK in register HWCTRL_REG will be set and the
MMICLK output is activated. If the timing generator
unit (SGU) is in Sleep mode, a wake-up request is
issued to force the SGU into the wake-up state. In the
wake-up state HWCTRL_INT and MMICLK are
activated. The MMIREQ flag has to be explicitly
cleared by the System Controller.
相關PDF資料 |
PDF描述 |
|---|---|
| PCF84C12A | 8-BIT MICROCONTROLLER |
| PCF84C12AP | 8-BIT MICROCONTROLLER |
| PCF84C12AT | 8-BIT MICROCONTROLLER |
| PCF84C21A | Telecom microcontrollers |
| PCF84C41A | Telecom microcontrollers |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PCF5083H/001/F2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC |
| PCF5083H/5V2/F3 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC |
| PCF5083H/F2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC |
| PCF51AC128ACFUE | 功能描述:32位微控制器 - MCU 32 Bit 128K FLASH 32K RAM CAN EN RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數據總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數據 RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT |
| PCF51AC128ACLKE | 功能描述:32位微控制器 - MCU 32 Bit 128K FLASH 32K RAM CAN EN RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數據總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數據 RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT |
發布緊急采購，3分鐘左右您將得到回復。