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參數資料
| 型號： | PCF5083 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | STEEL COVER |
| 中文描述： | GSM信號處理IC |
| 文件頁數： | 29/136頁 |
| 文件大小： | 602K |
| 代理商： | PCF5083 |
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1996 Oct 29
29
Philips Semiconductors
Objective specification
GSM signal processing IC
PCF5083
During the three level measurement mode the burst length
of the receive burst during the TX slot is defined by the
same register RXBURSTx_REG as used for the
MON burst. The receive frequency must be set by
programming the TX channel of the RF_IC interface.
For a certain operation mode in frame N, the Timing
Generator has to be programmed with all necessary
parameters in frame N
1. For this purpose the registers
RXSTART_REG, TXSTART_REG, MONSTART_REG
and MODEx_REG have an additional pipelining stage.
The pipelining takes place at the beginning of every TDMA
frame with the frame interrupt generation.
8.3.3
S
LEEP MODE
The Sleep mode circuitry is used to reduce the power
consumption during the Idle mode. During Sleep mode,
the mobile is switched on, but no call is active. The mobile
is only activated to read the paging blocks and for
neighbour cell monitoring. Outside these intervals, all ICs
can be switched off to save power.
In this mode also the main 13 MHz oscillator may be
switched off. To maintain TDMA timing alignment, the
PCF5083 is running temporarily on a slower clock
frequency, derived from the 32.768 kHz real time clock
oscillator. This clock is called Sleep Clock (SLCLK).
During the Sleep mode the PCF5083 controls the signals
specified in Table 15, the timing for these signals is
detailed in Table 16.
Sleep mode is activated with
QBCCTRL_REG[SLEEP] = 1 and
QBCCTRL_REG[SLEEPRED] = 0 (the SLEEPRED flag is
used for reduced Sleep mode, see below). The register
SLEEPCNT_REG has to be programmed with the number
of TDMA frames the mobile wants to sleep minus one.
Register FRAMECNT_REG is automatically cleared when
the Sleep mode is entered and counts the number of
TDMA frames actually slept. The 9-bit registers
SLEEPCNT_REG and FRAMECNT_REG allow a
maximum Sleep mode period of 512 frames. Refer to
Fig.11 for the signal flow.
Table 15
Signals controlled by the PCF5083 during Sleep mode
Table 16
Sleep mode signal timing
Notes
1.
(N)REFON is not deactivated if the Sleep mode is initiated while the sleep clock calibration procedure is running (see
Section 8.3.3.3), while the IOM
-2 interface is enabled or the MMICLK flag in register HWCTRL_REG is set,
indicating that the MMI controller requires the 13 MHz clock.
Maximum 295 ms before Sleep mode terminates with 4.6 ms resolution {[(0 to 63) + 1]
×
4.6 ms}.
2.
SIGNAL
DESCRIPTION
REFON
NREFON
DSPON
GPON1
GPON2
Reference oscillator on. Active HIGH output.
Inverted REFON output.
DSP power-down (connected on chip).
General purpose power-down and radio part interface 3-state enable. Active HIGH output.
General purpose power-down. Active HIGH output.
SIGNAL
FRAME NUMBER
ACTIVATION OF SIGNAL IF
SLEEPCNT_REG EQUALS
(N)REFON
DSPON
GPON1
GPON2
In frame N + 1 on the third positive SLCLK edge
In frame N + 1 on the second positive SLCLK edge
In frame N + 1 on the second positive SLCLK edge
In frame N + 1 on the third positive SLCLK edge
REFON_REG (notes 1 and 2)
KISSON_REG (note 2)
GPON1_REG (note 2)
GPON2_REG (note 2)
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相關代理商/技術參數 |
參數描述 |
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| PCF5083H/001/F2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC |
| PCF5083H/5V2/F3 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC |
| PCF5083H/F2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:GSM signal processing IC |
| PCF51AC128ACFUE | 功能描述:32位微控制器 - MCU 32 Bit 128K FLASH 32K RAM CAN EN RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數據總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數據 RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT |
| PCF51AC128ACLKE | 功能描述:32位微控制器 - MCU 32 Bit 128K FLASH 32K RAM CAN EN RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數據總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數據 RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT |
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