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參數資料
型號: PCF5083
廠商: NXP Semiconductors N.V.
英文描述: STEEL COVER
中文描述: GSM信號處理IC
文件頁數: 99/136頁
文件大小: 602K
代理商: PCF5083
1996 Oct 29
99
Philips Semiconductors
Objective specification
GSM signal processing IC
PCF5083
10 MICROCONTROLLER INTERFACE
The PCF5083 includes a standard 68000 compatible microcontroller interface. The interface consists of the lines
specified in Table 76.
The 128-byte wide register space of the Timer core is selected if HCEN_T is asserted. The 4 byte wide register space
of the DSP core is selected if HCEN_D is asserted. The DSP core only uses the address lines HA0 and HA1. All other
address lines are don’t care for the DSP core.
The Timer core accessed via HCEN_T does not assert DTACK.
Registers wider than 8-bit are aligned on word boundaries with the MSB on the lowest address and the LSB on the
highest address. For registers which use only three byte addresses, a reserved address location is provided to make
these registers accessible as longwords.
Reserved address locations, write only bits or registers and unused bits within registers are read as zeros and don’t care
for write operations.
For the DSP Core refer to Section 9.1.6.
Table 76
The Interface signal lines
10.1
Register Set for the Timer Core
Table 77
Register set
SIGNAL
DESCRIPTION
HD0 to HD7
HA0 to HA6
HR/W
HCEN_T
HCEN_D
DTACK
8-bit bidirectional data bus.
7-bit unidirectional address bus.
Read/write select line. A logic 0, writes to the PCF5083. A logic 1, reads from the PCF5083.
Chip select line for the Timer core (active LOW).
Chip select line for the DSP core (active LOW).
DSP core data acknowledge line (connected to the DTACK input of a 68000 compatible
microcontroller.
OFFSET
REGISTER
SIZE
R/W
(1)
DESCRIPTION
00, 01
02, 03
04
05
06
07
08
09
0A, 0B
0C, 0D
0E, 0F
10, 11
12
MODE0_REG
MODE1_REG
RXBURST0_REG
RXBURST1_REG
RXBURST2_REG
TXBURST0_REG
TXBURST1_REG
TXBURST2_REG
TXSTART_REG
MONSTART_REG
TXKEY0_REG
TXKEY1_REG
GPON1_REG
14
14
8
8
8
8
8
7
11
13
10
10
6
R/W
R/W
W
W
W
W
W
W
W
W
W
W
W
Mode Control Register 0; see Table 78
Mode Control Register 1; see Table 78
RXON length in bit
RXON length in bit
RXON length in bit
TXON length in bit
TXON length in bit
Start of the Rx burst in QB
Start of the TX burst in QB
Start of the MON burst in QB
TXKEY0 length in QB
TXKEY1 length in QB
Time of GPON1 getting active in TDMA frames before the end
of the Sleep mode
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