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參數資料
型號: AD9854
廠商: Analog Devices, Inc.
元件分類: XO, clock
英文描述: CMOS 300MHz Quadrature Complete-DDS
中文描述: 300MHz CMOS正交DDS數字合成器
文件頁數: 12/28頁
文件大小: 589K
代理商: AD9854
AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
register address 21 – 24 hex. Default values
of frequency, phase and amplitude are all zero.
To set the output amplitudes to full-scale (not
adjustable) change the
OSK EN
, address 20
hex, bit to logic low (see amplitude discussion
under previous
Shaped Keying
heading).
7/16/99 REV.PRA
12
As with all Analog Devices DDS’s, the value
of the frequency tuning word is determined
using the following equation:
FTW =
(desired output frequency * 2
N
)
/
SYSCLK
.
Where N is the phase accumulator resolution
(48 bits in this instance), frequency is
expressed in Hertz, and the FTW, frequency
tuning word, is a decimal number. Once a
decimal number has been found, it must be
converted to binary format – a series of 48
binary-weighted 1’s OR 0’s. he fundamental
output frequency range is from dc to
SYSCLK.
Phase adjust Register #2 and Frequency
Tuning Word #2 are not accessible in this
mode. Pin 29, “FSK, BPSK,HOLD”, has no
effect.
The I and Q DAC’s are always 90 degrees
out-of-phase. Changing the value in the Phase
Adjust Register 1 as suggested above will
change the phase of both I and Q DAC’s
simultaneously and by the same amount so that
both are at some phase offset relative to some
other event.
Changes in frequency are phase continuous –
that is, the new frequency uses the last phase
of the old frequency as a reference point to
compute the first new frequency phase.
FSK Mode:
When selected, the output
frequency of the DDS is a function of the
values loaded into Frequency Tuning Word
registers 1 & 2 AND the logic level of Pin 29.
A logic low on Pin 29 (FSK/BPSK/HOLD)
chooses F1 (frequency tuning word 1, address
4 – 9 hex) and a logic high chooses F2
(frequency tuning word 2, register address A –
F hex). Changes in frequency are practically
instantaneous and phase continuous. Other
than F2 and Pin 29 becoming active, this mode
is identical to single-tone.
BPSK Mode:
Abbreviation for binary, bi-
phase or bipolar-phase-shift-keying. Nearly
identical to the FSK mode except P1 (14-bit
phase tuning word 1, register address 0 – 1
hex) and P2 (phase tuning word 2, register
address 2 – 3 hex) are selected according to
the logic state of Pin 29. The output
frequency is set in frequency tuning word 1
registers. The 14-bit phase values range from
all 0’s = 0 degrees offset to all 1’s = 359.978
degrees offset. The value of 1 LSB is
360/16384 or .022033691 degrees. Phase
offsets apply equally to both the I and Q
outputs (unless the Q DAC is configured as an
auxiliary DAC)
Ramped FSK:
A method of FSK
whereby changes from F1 to F2 are
not instantaneous but instead are
accomplished in a frequency sweep or
“ramping” fashion. This means that
many intermediate frequencies may be
output in addition to the primary F1
and F2. The purpose of ramped FSK
is to provide better bandwidth
containment by “softening” the
instantaneous frequency changes with
gradual changes. The dwell time at F1
and F2 can be much greater than those
of the intermediate frequencies or
equal to the time spent at each of the
intermediate frequencies. Unlike
unramped FSK, ramped FSK requires
the lowest frequency to be loaded into
F1 registers and the highest frequency
into F2 registers.
Several registers must be programmed to
instruct the DDS regarding the resolution of
intermediate frequency steps and the time spent
at each step.
Register addresses 1A – 1C hex comprise the
Ramp Rate Clock
” register. This is a
count-down counter that outputs a pulse
whenever the count reaches zero. This counter
is being clocked at the System Clock Rate, 300
MHz maximum, and it operates exactly as the
8-bit ramp rate counter described in the
previous section labeled “Shaped On-Off
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