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參數(shù)資料
| 型號： | AD9854 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | CMOS 300MHz Quadrature Complete-DDS |
| 中文描述： | 300MHz CMOS正交DDS數(shù)字合成器 |
| 文件頁數(shù)： | 7/28頁 |
| 文件大小： | 589K |
| 代理商： | AD9854 |
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AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
Table I. AD9854 PIN FUNCTION DESCRIPTIONS…CONTINUED
7/16/99 REV.PRA
7
SCLK
Pin 21. Serial clock signal associated with the serial programming bus. Data is registered on the rising edge.
This pin is shared with WRB when the parallel mode is selected.
Pin 22. Chip-select signal associated with the serial programming bus. Active LOW. This pin is shared with
RDB when the parallel mode is selected.
Pin 70. Selects between Serial Programming mode (logic LOW) and Parallel Programming mode (logic HIGH)
CSB
S/P
SELECT
I/O UD
Pin 20. Bi-directional frequency update signal. Direction is selected in Control Register. If selected as an
input, a rising edge will transfer the contents of the programming registers to the internal works of the IC for
processing. If I/O UD is selected as an output, an output pulse (low to high) of 8 system clock cycle duration
indicates that an internal frequency update has occurred.
Pin 29. Multi-function pin according the mode of operation selected in the programming control register. If in
the FSK mode logic low selects F1, logic high selects F2. If in the BPSK mode, logic low selects phase 1, logic
high selects phase 2. If in the CHIRP mode, logic high engages the HOLD function which will cause the
frequency accumulator to halt at its current location. To resume or commence CHIRP, logic low is asserted.
Pin 30. Must first be selected in the programming control register to function. A logic high will cause the I &
Q DAC outputs to ramp-up from zero-scale to full-scale amplitude at a pre-programmed rate. Logic low causes
the full-scale output to ramp-down to zero-scale at the pre-programmed rate.
Pin 61. Connection for external series RC loop filter to Vdd. Recommended component values 1.3k and .01
μ
F.
FSK/BPSK/
HOLD
SHAPED
KEYING
PLL
FILTER
Synthesizer Functional Description
Internal & External Update Clock –
This function is
comprised of a bi-directional I/O pin, Pin 20, and a
programmable 32-bit down-counter.
In order for
programming changes to be transferred from the I/O
Buffer registers to the active core of the DDS, a clock
signal (low to high edge) must be externally supplied
to Pin 20 or internally generated by the 32-bit Update
Clock.
An externally generated Update Clock is internally
synchronized with the system clock to prevent partial
transfer of program register information due to
violation of data setup or hold times. This mode gives
the user complete control of when updated program
information becomes effective. The default mode is set
for internal update clock (Int Update Clk control
register bit is logic high). To switch to external update
clock mode, the Int Update Clk register bit must be set
to logic low. The internal update mode generates
automatic, periodic update pulses whose time period is
set by the user.
An internally generated Update Clock can be
established by programming the
32-bit Update Clock
registers (address 16-19 hex) and setting the
Int
Update Clk
(address 1F hex) control register bit to
logic high. The update clock down-counter function
operates at the system clock/2 (150 MHz maximum)
and counts down from a 32-bit binary value
(programmed by the user). When the count reaches 0,
an automatic I/O Update of the DDS output or
functions is generated. The update clock is routed
internally and externally on Pin 20 to allow users to
synchronize programming of update information with
the update clock rate. The time period between update
pulses is given as
(N+1) *(SYSTEM CLOCK
PERIOD/2),
where N is the 32-bit value programmed
by the user. Allowable range of N is from 1 to (2
32
–
1). The internally generated Update pulse output on
Pin 20 has a fixed duration of ten system clock cycles
Shaped On-Off Keying
– Allows user to control the
ramp-up and ramp-down time of an “on-off” emission
from the I and Q DACs. This function is used in “burst
transmissions” of digital data to reduce the adverse
spectral impact of short, abrupt bursts of data. Users
must first enable the digital multipliers by setting the
OSK EN
bit (control register address 20 hex) to logic
high in the control register. Otherwise, if
OSK EN
bit
is set low, the digital multipliers responsible for
amplitude-control are by-passed and the I and Q DAC
outputs are set to full-scale amplitude.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9854/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For IC Digital Synthesizer Single 制造商:Analog Devices 功能描述:Direct Digital Synthesizer IC (DDS) |
| AD9854/PCBZ | 功能描述:BOARD EVAL FOR AD9854 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:AgileRF™ 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| AD9854ASQ | 制造商:Analog Devices 功能描述:IC DDS SYNTHESIZER |
| AD9854ASQZ | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP 制造商:Analog Devices 功能描述:Communication IC |
| AD9854AST | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP Tray 制造商:Rochester Electronics LLC 功能描述:200 MHZ QUADRATURE DDS SYNTHESIZER - Tape and Reel 制造商:Analog Devices 功能描述:IC SEMICONDUCTOR ((NS)) |
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