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參數(shù)資料
| 型號： | AD9854 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | CMOS 300MHz Quadrature Complete-DDS |
| 中文描述： | 300MHz CMOS正交DDS數(shù)字合成器 |
| 文件頁數(shù)： | 26/28頁 |
| 文件大小： | 589K |
| 代理商： | AD9854 |
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AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
7/16/99 REV.PRA
26
Data read cycle, 3-wire configuration, SCLK IDLE Low
CS
SCLK
SDIO
IR WRITE PHASE
DATA TRANSFER - TWO BYTE READ
I0
I1 I2
I3
I4
I5
I6
I7
B0
B1 B2
B3
B4
B5
B6
B7
B8
B9 B10 B11 B12 B13 B14 B15
SDO
MSB/LSB Transfers
The AD9854/52 serial port can support both most
significant bit (MSB) first or least significant bit (LSB)
first data formats. This functionality is controlled by the
REG0<6> bit. When REG0<6> is set active high, the
AD9854/52 serial port is in LSB first format. REG0<6>
defaults low, to the MSB first format. The instruction byte
must be written in the format indicated by REG0<6>. That
is, if the AD9854/52 is in LSB first mode, the instruction
byte must be written from least significant bit to most
significant bit.
Multi-byte data transfers in MSB format can be completed
by writing an instruction byte which includes the register
address of the most significant byte. In MSB first mode,
the serial port internal byte address generator decrements
for each byte required of the multi-byte communication
cycle. Multi-byte data transfers in LSB first format can be
completed by writing an instruction byte which includes
the register address of the least significant byte. In LSB
first mode, the serial port internal byte address generator
increments for each byte required of the multi-byte
communication cycle.
Update Clock Operation
Programming the AD9854/52 is asynchronous to the
system clock with all data being stored in a buffer memory
that does not immediately affect the part operation. The
buffer memory is transferred to the register bank
synchronous to system clock. The register bank
information affects part operation.
This transfer of data can occur automatically, with
frequency of updates programmable by the user, or can
occur completely under user control.
Complete user control, referred to as external update mode,
allows the user to drive the UPDATE_CLK signal from
their ASIC or DSP. The AD9854/52 UPDATE_CLK pin
is configured as an input in external update mode. A rising
edge on UPDATE_CLK indicates to the AD9854/52 that
the contents of the buffer memory is to be transferred to the
register bank. The design uses an edge detector to signal
the AD9854/52 to transfer data which allows a very small
minimum high pulse width requirement (two system clock
periods). Its important to note that if the user keeps
UPDATE_CLK high, the AD9854/52 will NOT
continuously update the register bank.
Internal update mode, in which the AD9854/52 transfers
data from the buffer memory to the register bank
automatically, configures the AD9854/52 UPDATE_CLK
pin as an output. The AD9854/52 generates a high pulse
on UPDATE_CLK pin to signal the user that the buffer
memory has just been transferred to the register bank. The
minimum high pulse width is designed to be 8 system
clock cycles (min). The UPDATE_CLK signal can be used
as an interrupt within the system. Its important to note that
as an output UPDATE_CLK pin will not have anything
approaching a 50/50 duty cycle for slower update rates.
Programming the Update Clock register for values less
than 5 will cause the UPDATE_CLOCK pin to remain
high. The update clock functionality still works, its just
that the user cannot use the signal as an indication that
data is transferring. This is an affect of the minimum high
pulse time when UPDATE_CLK is an output.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9854/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For IC Digital Synthesizer Single 制造商:Analog Devices 功能描述:Direct Digital Synthesizer IC (DDS) |
| AD9854/PCBZ | 功能描述:BOARD EVAL FOR AD9854 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:AgileRF™ 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| AD9854ASQ | 制造商:Analog Devices 功能描述:IC DDS SYNTHESIZER |
| AD9854ASQZ | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP 制造商:Analog Devices 功能描述:Communication IC |
| AD9854AST | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP Tray 制造商:Rochester Electronics LLC 功能描述:200 MHZ QUADRATURE DDS SYNTHESIZER - Tape and Reel 制造商:Analog Devices 功能描述:IC SEMICONDUCTOR ((NS)) |
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