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參數資料
| 型號： | AD9854 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | CMOS 300MHz Quadrature Complete-DDS |
| 中文描述： | 300MHz CMOS正交DDS數字合成器 |
| 文件頁數： | 14/28頁 |
| 文件大小： | 589K |
| 代理商： | AD9854 |
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AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
Finally, two more control bits are available to allow
even more options.
CLR ACC1
,
7/16/99 REV.PRA
14
register address 1F hex, if set high will clear
the frequency accumulator (Acc 1) output with
a one-shot pulse of one system clock duration.
The effect is to interrupt the current ramp,
reset the frequency back to the start point, F1,
and then continue to ramp up at the previous
rate. Next,
CLR ACC2
control bit (register
address 1F hex) is available to clear the phase
accumulator (ACC 2). When this bit is set
high, the output of ACC2 is set to zero
resulting in 0 Hz output from the DDS at a
phase angle existing just before the CLR
ACC2 bit was set to logic high. As long as
this bit is set high, the phase accumulator will
be cleared and 0 Hertz will be output. To
resume normal DDS operation, CLR ACC2
must be logic low.
FM CHIRP –
Allows precise, internally
generated linear or non-linear FM over a user
defined frequency range, duration, frequency
resolution and sweep direction(s). The user
programs a start or base frequency into
Frequency Tuning Word 1 (register address 4
– 9 hex), the frequency step resolution into the
48-bit Delta Frequency Word (register address
10 – 15 hex) and rate of change into the 20-bit
Ramp Rate Clock (Register address 1A – 1C).
Chirp stops on a HOLD command, logic high
on Pin 29, or when a value of 0 is loaded as a
Delta Frequency Word. In this state, the output
frequency remains at the frequency just before
the halting action was asserted.
Several control bits permit numerous options
in the Chirp mode. Any of these options may
use either linear or non-linear frequency
progression. The control bits that provide these
options are: CLR ACC1, CLR ACC2, INT
UPDATE CLK, OSK EN, OSK INT. The
following is a brief description of what these
control bits do:
1)
CLR ACC1 control bit causes the output
of the 48-bit Frequency Accumulator to be
set to zero for one system clock period.
The effect is to return the Chirp signal to
its origin (F1). This is similar to a re-
triggerable one-shot event. As long as
CLR ACC1 bit is logic high, a zeroing of
the frequency accumulator output will
occur on every Update Clock rising edge.
After the accumulator has been zeroed, it
will
resume
normal
functions using all-zeros as the beginning
point. This bit defaults to logic low, which
prevents
zeroing
accumulator from this source.
accumulation
of
the
frequency
2)
CLR ACC2 control bit causes the output
of the 48-bit Phase Accumulator to be zero’ed.
This causes the output frequency to go to 0
Hertz as long as this control bit is set to logic
high. In addition, this results in a zeroing of
the Frequency Accumulator. The condition
persists for both accumulators until the CLR
ACC2 bit is returned to logic low (default
value). Upon return to logic low, the DDS
output
will
return
programmed into Frequency Tuning Word 1
registers (F1) and the chirp will resume as
previously programmed.
to
the
frequency
3)
The UPDATE CLK control bit allows
precisely timed Update Clock pulses to be
internally generated according to the setting of
the 32-bit Update Clock down-counter
described on page 6. Between internally
generated update clock pulses, the user can
write changes to the program registers that will
take effect upon receipt of a new update pulse.
Pin 20, I/O UD, will be pulsed high for 10
system clock cycles as evidence that an
internal update has occurred. This is
especially useful for non-linear Chirp where
intensive programming of various registers is
required.
4)
OSK EN and the OSK INT control bits
allow users to control the amplitude of the
DDS output either directly via the parallel or
serial port and automatically using the 8-bit
Ramp Rate down-counter and 12 bit up-
counter. The registers associated with these
control bits and logic states controlling these
bits are covered in the “Shaped On-Off
Keying” section of this preliminary data sheet.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9854/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For IC Digital Synthesizer Single 制造商:Analog Devices 功能描述:Direct Digital Synthesizer IC (DDS) |
| AD9854/PCBZ | 功能描述:BOARD EVAL FOR AD9854 RoHS:是 類別:編程器，開發系統 >> 評估演示板和套件 系列:AgileRF™ 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| AD9854ASQ | 制造商:Analog Devices 功能描述:IC DDS SYNTHESIZER |
| AD9854ASQZ | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP 制造商:Analog Devices 功能描述:Communication IC |
| AD9854AST | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP Tray 制造商:Rochester Electronics LLC 功能描述:200 MHZ QUADRATURE DDS SYNTHESIZER - Tape and Reel 制造商:Analog Devices 功能描述:IC SEMICONDUCTOR ((NS)) |
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