- 您現在的位置：買賣IC網 > PDF目錄373969 > AD9854 (Analog Devices, Inc.) CMOS 300MHz Quadrature Complete-DDS PDF資料下載
參數資料
| 型號： | AD9854 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | CMOS 300MHz Quadrature Complete-DDS |
| 中文描述： | 300MHz CMOS正交DDS數字合成器 |
| 文件頁數： | 27/28頁 |
| 文件大小： | 589K |
| 代理商： | AD9854 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當前第27頁第28頁
AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
7/16/99 REV.PRA
27
For internal update clock operation, the rate which the
updates occur is programmed into the update clock
register. The update clock register is 32 bits and the value
written into the register corresponds to HALF the number
of clock cycles between updates. That is, if a value of
00_00_00_0a (hex), is written into the update clock
register the rising edge of the UPDATE_CLOCK pin will
occur every 20 cycles (0a hex equals 10 decimal).
Control Register
The Control Register is located in the shaded portion of the
Register Layout table at address 1D through 20 hex. It is
composed of 32 bits. Bit 31 is located at the top left
position and bit 0 is located in the lower right position of
the shaded table portion. The register has been sub-
divided below to make it easier to locate the text associated
with specific control categories.
Power down functions:
Four bits are available to power down the AD9854/52.
Each bit is active high, that is, they default low and a logic
1 causes the power down function to be working, The four
bits all reside in the same control byte such that one IO
write cycle can complete a full power down by writing all
four bits true simultaneously. The four bits are located in
Control Register[28, 26:24] and are described below. The
default state for these bits is logic zero, inactive.
CR[31:29] are open
CR[28] is the comparator power down bit. When set (logic
1), this signal indicates to the comparator that a power
down mode is active. This bit is an output of the digital
section and is an input to the analog section.
CR[27] must always be written to logic zero. Writing this
bit to logic one causes the AD9854/52 to stop working
until a master reset is applied.
CR[26] is the Q DAC power down bit. When set (logic 1),
this signal indicates to the Q DAC a power down mode is
active. This bit is an out of the digital section and is an
input to the analog section.
CR[25] is the full DAC power down bit. When set (logic
1), this signal indicates to both the I and Q dacs as well as
the reference that a power down mode is active. This bit is
an out of the digital section and is an input to the analog
section.
CR[24] is the digital power down bit. When set (logic 1),
this signal indicates to the digital section that a power
down mode is active. Within the digital section, the clocks
will be forced to DC, effectively powering down the digital
section. The REFCLK input will still be seen by the PLL
and the PLL will continue to output the higher frequency.
PLL functions:
Seven Control register bits, located in the Control
Register[22:16] positions, relate to the PLL.
CR[23] is open
CR[22] is the PLL range bit. The PLL range bit controls
the VCO gain. The power up state of the PLL range bit is
logic 1, higher gain for high frequencies.
CR[21] is the bypass PLL bit, active high. When active the
PLL is powered down and the REFCLK input is used to
drive the system clock signal. The power up state of the
bypass PLL bit is logic 1, PLL bypassed.
CR[20:16] bits are the PLL multiplier factor. These bits are
the REFCLK multiplication factor unless the bypass PLL
bit is set. The PLL multiplier valid range is from 4 to 20,
inclusive.
Other operational functions:
CR[15] is the clear accumulator 1 bit. This bit has a one
shot type function. When written active, logic one, a clear
accumulator 1 signal is sent to the DDS logic, resetting the
accumulator value to zero. The bit is then automatically
reset but the buffer memory is not reset. This bit allows the
user to easily create a saw wave output with very little (or
no) user input required. This bit is intended for chirp mode
only but there is no logic to suppress its functionality in
other modes.
CR[14] is the clear accumulators bit. This bit, active high,
holds both the accumulator 1 and accumulator 2 values at
zero for as long as the bit is active. This allows the DDS
phase to be initialized via the IO port.
CR[13] is the triangle bit. When this bit is set the
AD9854/52 will automatically perform a continuous
frequency sweep from the mark to space frequencies and
back. The effect is a triangular frequency sweep. When this
bit is set, the operating mode must be set to ramped fsk.
CR[12] is the source Q DAC bit on the AD9854 only.
When set, the Q path DAC accepts data from the QDAC
Register. For the AD9852, this bit does not require a logic
one as the only data available to the Q path DAC is from
the QDAC Register.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9858TLPCB | 1 GSPS Direct Digital Synthesizer |
| AD9858BSV | 1 GSPS Direct Digital Synthesizer |
| AD9858PCB | 1 GSPS Direct Digital Synthesizer |
| AD9858 | 1 GSPS Direct Digital Synthesizer |
| AD9858FDPCB | 1 GSPS Direct Digital Synthesizer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9854/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For IC Digital Synthesizer Single 制造商:Analog Devices 功能描述:Direct Digital Synthesizer IC (DDS) |
| AD9854/PCBZ | 功能描述:BOARD EVAL FOR AD9854 RoHS:是 類別:編程器，開發系統 >> 評估演示板和套件 系列:AgileRF™ 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| AD9854ASQ | 制造商:Analog Devices 功能描述:IC DDS SYNTHESIZER |
| AD9854ASQZ | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP 制造商:Analog Devices 功能描述:Communication IC |
| AD9854AST | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP Tray 制造商:Rochester Electronics LLC 功能描述:200 MHZ QUADRATURE DDS SYNTHESIZER - Tape and Reel 制造商:Analog Devices 功能描述:IC SEMICONDUCTOR ((NS)) |
發布緊急采購，3分鐘左右您將得到回復。