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參數資料
| 型號： | AD9854 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | CMOS 300MHz Quadrature Complete-DDS |
| 中文描述： | 300MHz CMOS正交DDS數字合成器 |
| 文件頁數： | 16/28頁 |
| 文件大小： | 589K |
| 代理商： | AD9854 |
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between zero and full-scale for static amplitude
adjustment. Both I and Q DAC amplitudes are
individually programmable. See the “Shaped On-Off
Keying” description for more information. This
function does not apply to the Q DAC when configured
as a Control DAC. In this instance, the user is in
control of the Control DAC output level via the 12-bit
QDAC register at address 26 and 27 hex of the
programming registers
High Speed Comparator
– optimized for high speed,
> 300 MHz toggle rate, low jitter, sensitive input,
built-in hysteresis and an output level of one Volt p-p
minimum into 50 ohms or CMOS logic levels into high
impedance loads. The comparator can be separately
powered-down to conserve power. This comparator is
used in “clock generator” applications to square-up a
bandpass or lowpass filtered sine wave.
Eight-bit Ramp Rate Clock –
when Shaped On-Off
Keying is engaged, this down-counter takes the system
clock (300 MHz maximum), and divides it by an 8-bit
binary value (programmed by the user) to produce a
user-defined clock. The clock outputs one pulse every
time the counter counts down to zero. This clock is
used to set the rate-of-change of the 12-bit digital
multipliers of the I & Q DACs to perform an output
shaping function.
Twenty-bit Ramp Rate Clock
– when selected, this
down-counter takes the system clock (300 MHz
maximum) and divides it by a 20-bit binary value
(programmed by the user) to produce a user-defined
clock. The clock outputs one pulse every time the
counter counts down to zero. This clock is used to set
the rate-of-frequency-change of the ramped FSK or
FM CHIRP modes. See Figure 1.
Forty-eight-bit Delta Frequency Register –
is used
only in the CHIRP and ramped FSK modes. This
register is loaded with a 48-bit word that represents the
frequency increment value of Frequency Accumulator
(ACCU 1) whose output will be added to a frequency
that is set in either F1 or F2 frequency registers. This
register is periodically incremented at a rate set by the
20-bit ramp rate clock (150 MHz maximum).
Forty-eight-bit Delta Phase Register –
is
programmed with a 48-bit Frequency Tuning Word
that is input to the 48-bit Phase Accumulator (ACCU
2) and determines the output frequency of the DDS in
the single-tone mode. When ramped-FSK or Chirp are
selected, this register is sent to a digital adder where it
is summed with the output of ACCU 1 before being
input to ACCU 2. Therefore, the signal sent to ACCU
2 may be either static or changing at a rate of up to
150 million 48-bit frequency tuning words per second.
Power-Down
- Several individual stages, when not
needed, can be powered-down to reduce power
consumption via the programming registers while still
maintaining functionality of desired stages. These
stages are identified in the Register Layout table,
address 1D hex. Power-down is achieved by setting
the specified bits to logic high. A logic low indicates
that the stages are powered-up
Furthermore, and perhaps most significantly, two
intensely digital stages, the Inverse Sinc filters and the
Digital Multiplier stages can be bypassed to achieve
significant power reduction through programming of
the control registers in address 20 hex. Again, logic
high will cause the stage to be by-passed. Of
particular importance is the Inverse Sinc filter. When
clocked at the maximum 300 MHz, this stage
consumes 1.5 watts. If low power consumption is a
critical factor then bypassing of the Inverse Sinc filter
will save 1.5 watts.
A full power-down occurs when all five PD Bits in
control register 1D hex are set to logic high. This
reduces power consumption to approximately 10 mW
(3 ma).
Master RESET –
logic high active, must be held high
for a minimum of 10 system clock cycles. Causes the
communications bus to be initialized and loads default
values listed in the Register Layout table.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9854/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For IC Digital Synthesizer Single 制造商:Analog Devices 功能描述:Direct Digital Synthesizer IC (DDS) |
| AD9854/PCBZ | 功能描述:BOARD EVAL FOR AD9854 RoHS:是 類別:編程器，開發系統 >> 評估演示板和套件 系列:AgileRF™ 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| AD9854ASQ | 制造商:Analog Devices 功能描述:IC DDS SYNTHESIZER |
| AD9854ASQZ | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP 制造商:Analog Devices 功能描述:Communication IC |
| AD9854AST | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP Tray 制造商:Rochester Electronics LLC 功能描述:200 MHZ QUADRATURE DDS SYNTHESIZER - Tape and Reel 制造商:Analog Devices 功能描述:IC SEMICONDUCTOR ((NS)) |
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