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參數資料
型號: AD9854
廠商: Analog Devices, Inc.
元件分類: XO, clock
英文描述: CMOS 300MHz Quadrature Complete-DDS
中文描述: 300MHz CMOS正交DDS數字合成器
文件頁數: 21/28頁
文件大?。?/td> 589K
代理商: AD9854
AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
AD9854/52 Parallel Port Read Timing Diagram
7/16/99 REV.PRA
21
Serial Port IO Operation
With the SPSELECT pin tied low, the serial IO mode
is active. T
he AD9854/52 serial port is a flexible,
synchronous serial communications port allowing easy
interface to many industry standard microcontrollers and
microprocessors. The serial I/O is compatible with most
synchronous transfer formats, including both the Motorola
6905/11 SPI and Intel 8051 SSR protocols. The interface
allows read/write access to all 12 registers that configure
the AD9854/52 and
can be configured as a single pin IO
(SDIO) or two unidirectional pins for in/out
(SDIO/SDO). Data transfers are supported in most
significant bit (msb) first format or least significant bit
(lsb) first format at up to 10Mhz.
When configured for serial IO operation, most pins
from the AD9854/52 parallel port are inactive; some
are used for the serial IO. Table x below describes pin
requirements for serial IO.
Pin Number
1,2,3,4,5,6,7,8
14,15,16
17
18
19
20
21
22
Pin Name
D[7:0]
A[5:3]
A2
A1
A0
I/O UD
WRB
RDB
Serial IO Description
The parallel data pins are not active, tie to VDD or GND
The parallel address pins A5, A4, A3 are not active, tie to VDD or GND
IORESET
SDO
SDIO
Update Clock. Same functionality for Serial Mode as Parallel Mode
SCLK
CSB – Chip Select
February 22, 1999
D<7:0>
A<5:0>
A
2
A
3
D
3
____
RD
Specification Value Description
T
ADV
tbd Address To Data Valid Time (maximum)
T
ADH
tbd Address Hold Time To RD Signal Inactive (minimum)
T
RDLOV
tbd RD Low to Output Valid (maximum)
T
RDHOZ
tbd RD High To Data Tristate (maximum)
D
2
A
1
T
AHD
D
1
T
RDHOZ
T
RDLOV
T
ADV
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