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參數(shù)資料
| 型號(hào)： | AD9854 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | CMOS 300MHz Quadrature Complete-DDS |
| 中文描述： | 300MHz CMOS正交DDS數(shù)字合成器 |
| 文件頁數(shù)： | 9/28頁 |
| 文件大小： | 589K |
| 代理商： | AD9854 |
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AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
Above: Block diagram of Q-pathway of the digital multiplier section responsible for Shaped Keying function.
The I-pathway is similar except no alternate 12-bit Q-DAC source register is provided.
7/16/99 REV.PRA
9
The two fixed elements are the clock period of the
system clock (that drives the Ramp Rate Counter) and
the 4096 amplitude steps between zero-scale and full-
scale. To give an example, assume that the System
Clock of the AD9854 is 100 MHz (10 ns period). If
the Ramp Rate Counter is programmed for a minimum
count of 1, it will take two system clock periods (one
rising edge loads the count-down value, the next edge
decrements the counter from 1 to zero). The
relationship of the 8-bit count-down value to the time
period between output pulses is given as:
(N+1) *
SYSTEM CLOCK PERIOD
, where N is the 8-bit
count-down value. It will take 4096 of these pulses to
advance the 12-bit up-counter from zero-scale to full-
scale. Therefore, the minimum shaped keying ramp
time for a 100 MHz system clock is 4096 * 2 * 10 ns
= approximately 82 microseconds. The maximum
ramp time will be 4096 * 256 * 10 ns * 4096 =
approximately 10.5 msec.
Finally, changing the logic stage of pin 30, “shaped
keying” will automatically perform the programmed
output envelope functions when OSK INT is high. A
logic high on Pin 30 causes the outputs to linearly
ramp-up to full-scale amplitude and hold until the logic
level is changed to low causing the outputs to ramp-
down to zero-scale.
I & Q DACs –
the 300 MSPS (maximum) sine and
cosine wave outputs of the DDS. Their maximum
output amplitudes are set by the DAC
R
SET
resistor at
pin 56. These are current-out DACs with a full-scale
maximum output of 20 mA; however, a nominal 10
mA output current provides best spurious-free dynamic
range (SFDR) performance. The value of R
SET
=
39.93/Iout, where Iout is in amps. DAC output
compliance specification limits the maximum voltage
developed at the outputs to -.5 to +1V. Voltages
developed beyond this limitation will cause excessive
DAC distortion and possibly permanent damage. The
user must choose a proper load impedance to limit the
output voltage swing to <= compliance limits. Both
DAC outputs should be terminated equally for best
SFDR, especially at higher output frequencies where
harmonic distortion is at its worst.
Both DACs are preceded by inverse SIN (X)/X filters
(a.k.a. inverse sinc filters) that pre-compensate for
DAC output amplitude variations over frequency to
achieve flat amplitude response from dc to Nyquist.
Digital multipliers follow the inverse sinc filters to
allow amplitude control, amplitude modulation and
amplitude shaped keying. The inverse sinc filters
(address 20 hex,
Bypass Inv Sinc
bit)) and digital
multipliers (address 20 hex,
OSK EN
bit) can be
bypassed for power conservation by setting those bits
high. Both DACs can be powered-down by setting the
DAC PD
bit high (address 1D of control register)
when not needed.
I-DAC outputs are designated as IOUT1 and IOUT1B,
pins 48 and 49 respectively. Q-DAC outputs are
designated as IOUT2 AND IOUT2B, pins 52 and 51
respectively.
Control DAC
–The 12- bit
Q DAC
can be
reconfigured to perform as a “control” or auxiliary
DAC as in the AD9852. The control DAC output can
provide DC control levels to external circuitry, AC
signals or enable pulse-width modulation (PWM), or
duty cycle control, of the on-board comparator when
appropriately configured in the clock generator
application. When the
SRC QDAC
bit in control
register (address 1F hex) is set high, the Q-DAC inputs
are switched from internal 12-bit Q data source
(default setting) to external 12-bit data supplied by the
user through the serial or parallel interface to the 12-bit
Q DAC register
(address 26 and 27 hex) at 100 MHz
(maximum) data rate. This DAC is clocked at the
system clock, 300 MSPS (maximum), and has the
same maximum output current capability as that of the
I DAC. The single R
SET
resistor on the AD9854 sets
the full-scale output current for both DACs. The
control DAC can be separately powered-down for
power conservation when not needed by setting the
Q
DAC POWER-DOWN
bit high (address 1D hex).
Control DAC outputs are designated as IOUT2 and
IOUT2B, pins 52 and 51 respectively.
Inverse SINC function
– this filter pre-compensates
input data to both DACs for the SIN (X)/X roll-off
function to allow wide bandwidth signals (such as
QPSK) to be output from the DACs without
appreciable amplitude variations that will cause
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD9854/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For IC Digital Synthesizer Single 制造商:Analog Devices 功能描述:Direct Digital Synthesizer IC (DDS) |
| AD9854/PCBZ | 功能描述:BOARD EVAL FOR AD9854 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:AgileRF™ 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| AD9854ASQ | 制造商:Analog Devices 功能描述:IC DDS SYNTHESIZER |
| AD9854ASQZ | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP 制造商:Analog Devices 功能描述:Communication IC |
| AD9854AST | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP Tray 制造商:Rochester Electronics LLC 功能描述:200 MHZ QUADRATURE DDS SYNTHESIZER - Tape and Reel 制造商:Analog Devices 功能描述:IC SEMICONDUCTOR ((NS)) |
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