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參數資料
| 型號： | AD9854 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | CMOS 300MHz Quadrature Complete-DDS |
| 中文描述： | 300MHz CMOS正交DDS數字合成器 |
| 文件頁數： | 24/28頁 |
| 文件大小： | 589K |
| 代理商： | AD9854 |
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AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
7/16/99 REV.PRA
24
Notes on Serial Port Operation
The AD9854/52 serial port configuration bits reside in bits
1 and 0 of register address 7h. It is important to note that
the configuration changes IMMEDIATELY upon writing
this register. For multibyte transfers, writing this register
may occur during the middle of a communication cycle.
Care must be taken compensate for this new configuration
for the remainder of the current communication cycle.
The system must maintain synchronization with the
AD9854/52 or the internal control logic will not be able to
recognize further instructions. For example, if the system
sends the instruction to write a 2-byte register, then pulses
the SCLK pin for a 3-byte register (24 additional SCLK
rising edges), communication synchronization is lost. In
this case, the first 16 SCLK rising edges after the
instruction cycle will properly write the first two data bytes
into the AD9854/52 but the next 8 rising SCLK edges are
interpreted as the next instruction byte, NOT the final byte
of the previous communication cycle.
In the case where synchronization is lost between the
system and the AD9854/52, the SYNC I/O pin provides a
means to re-establish synchronization without re-
initializing the entire chip. Asserting the SYNC I/O pin
(active high) resets the AD9854/52 serial port state
machine, terminating the current IO operation and putting
the device into a state in which the next 8 SCLK rising
edges are understood to be an instruction byte. The SYNC
IO pin must be de-asserted (low) before the next
instruction byte write can begin. Any information that had
been written to the AD9854/52 registers during a valid
communication cycle prior to loss of synchronization will
remain intact.
Timing Diagram for Data Write to AD9854/52
t
PRE
t
SCLK
t
DSU
SCLK
SDIO
t
SCLKPWH
t
SCLKPWL
t
DHLD
1st Bit
2nd Bit
CS
SYMBOL
t
PRE
t
SCLK
t
DSU
t
SCLKPWH
t
SCLKPWL
t
DHLD
DEFINITION
CS Set up Time
Period of Serial Data Clock
Serial Data Set up Time
Serial Data Clock Pulse Width High
Serial Data Clock Pulse Width Low
Serial Data Hold Time
MIN
30 ns
100 ns
30 ns
40 ns
40 ns
0 ns
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9854/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For IC Digital Synthesizer Single 制造商:Analog Devices 功能描述:Direct Digital Synthesizer IC (DDS) |
| AD9854/PCBZ | 功能描述:BOARD EVAL FOR AD9854 RoHS:是 類別:編程器，開發系統 >> 評估演示板和套件 系列:AgileRF™ 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| AD9854ASQ | 制造商:Analog Devices 功能描述:IC DDS SYNTHESIZER |
| AD9854ASQZ | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP 制造商:Analog Devices 功能描述:Communication IC |
| AD9854AST | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP Tray 制造商:Rochester Electronics LLC 功能描述:200 MHZ QUADRATURE DDS SYNTHESIZER - Tape and Reel 制造商:Analog Devices 功能描述:IC SEMICONDUCTOR ((NS)) |
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